Age | Commit message (Expand) | Author | Files | Lines |
2021-11-02 | target/mips: Convert MSA ELM instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -13/+52 |
2021-11-02 | target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) | Philippe Mathieu-Daudé | 2 | -863/+106 |
2021-11-02 | target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) | Philippe Mathieu-Daudé | 2 | -34/+9 |
2021-11-02 | target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) | Philippe Mathieu-Daudé | 2 | -158/+35 |
2021-11-02 | target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) | Philippe Mathieu-Daudé | 2 | -12/+11 |
2021-11-02 | target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) | Philippe Mathieu-Daudé | 2 | -176/+76 |
2021-11-02 | target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) | Philippe Mathieu-Daudé | 2 | -39/+38 |
2021-11-02 | target/mips: Convert MSA VEC instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -75/+31 |
2021-11-02 | target/mips: Convert MSA 2R instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -75/+19 |
2021-11-02 | target/mips: Convert MSA FILL opcode to decodetree | Philippe Mathieu-Daudé | 2 | -12/+21 |
2021-11-02 | target/mips: Convert MSA 2RF instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -85/+53 |
2021-11-02 | target/mips: Convert MSA load/store instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -59/+36 |
2021-11-02 | target/mips: Convert MSA I8 instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -56/+27 |
2021-11-02 | target/mips: Convert MSA SHF opcode to decodetree | Philippe Mathieu-Daudé | 2 | -17/+22 |
2021-11-02 | target/mips: Convert MSA BIT instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -97/+101 |
2021-11-02 | target/mips: Convert MSA I5 instruction format to decodetree | Philippe Mathieu-Daudé | 2 | -77/+41 |
2021-11-02 | target/mips: Convert MSA LDI opcode to decodetree | Philippe Mathieu-Daudé | 2 | -9/+21 |
2021-11-02 | target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v | Philippe Mathieu-Daudé | 2 | -18/+17 |
2021-11-02 | target/mips: Use enum definitions from CPUMIPSMSADataFormat enum | Philippe Mathieu-Daudé | 1 | -3/+3 |
2021-11-02 | target/mips: Have check_msa_access() return a boolean | Philippe Mathieu-Daudé | 1 | -7/+18 |
2021-11-02 | target/mips: Use dup_const() to simplify | Philippe Mathieu-Daudé | 1 | -20/+3 |
2021-11-02 | target/mips: Adjust style in msa_translate_init() | Philippe Mathieu-Daudé | 1 | -1/+3 |
2021-11-02 | target/mips: Fix MSA MSUBV.B opcode | Philippe Mathieu-Daudé | 1 | -16/+16 |
2021-11-02 | target/mips: Fix MSA MADDV.B opcode | Philippe Mathieu-Daudé | 1 | -16/+16 |
2021-10-18 | target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() | Philippe Mathieu-Daudé | 1 | -4/+0 |
2021-10-18 | target/mips: Fix DEXTRV_S.H DSP opcode | Philippe Mathieu-Daudé | 1 | -2/+1 |
2021-10-18 | target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() | Philippe Mathieu-Daudé | 1 | -3/+1 |
2021-10-18 | target/mips: Use explicit extract32() calls in gen_msa_i5() | Philippe Mathieu-Daudé | 1 | -7/+4 |
2021-10-18 | target/mips: Use tcg_constant_i32() in gen_msa_3rf() | Philippe Mathieu-Daudé | 1 | -9/+14 |
2021-10-18 | target/mips: Use tcg_constant_i32() in gen_msa_2r() | Philippe Mathieu-Daudé | 1 | -3/+2 |
2021-10-18 | target/mips: Use tcg_constant_i32() in gen_msa_2rf() | Philippe Mathieu-Daudé | 1 | -2/+1 |
2021-10-18 | target/mips: Use tcg_constant_i32() in gen_msa_elm_df() | Philippe Mathieu-Daudé | 1 | -2/+1 |
2021-10-18 | target/mips: Remove unused register from MSA 2R/2RF instruction format | Philippe Mathieu-Daudé | 1 | -6/+0 |
2021-10-17 | target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 | Philippe Mathieu-Daudé | 1 | -0/+6 |
2021-10-15 | target/mips: Drop exit checks for singlestep_enabled | Richard Henderson | 1 | -32/+18 |
2021-10-15 | target/mips: Fix single stepping | Richard Henderson | 1 | -9/+16 |
2021-10-13 | target/mips: Use 8-byte memory ops for msa load/store | Richard Henderson | 1 | -130/+71 |
2021-10-13 | target/mips: Use cpu_*_data_ra for msa load/store | Richard Henderson | 1 | -285/+135 |
2021-10-05 | tcg: Rename TCGMemOpIdx to MemOpIdx | Richard Henderson | 1 | -3/+3 |
2021-09-21 | hw/core: Make do_unaligned_access noreturn | Richard Henderson | 1 | -2/+2 |
2021-09-14 | target/mips: Restrict cpu_exec_interrupt() handler to sysemu | Philippe Mathieu-Daudé | 4 | -25/+21 |
2021-09-14 | accel/tcg: Add DisasContextBase argument to translator_ld* | Ilya Leoshkevich | 4 | -9/+9 |
2021-08-25 | target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() | Philippe Mathieu-Daudé | 3 | -45/+50 |
2021-08-25 | target/mips: Store CP0_Config0 in DisasContext | Philippe Mathieu-Daudé | 2 | -0/+2 |
2021-08-25 | target/mips: Replace GET_LMASK64() macro by get_lmask(64) function | Philippe Mathieu-Daudé | 1 | -19/+16 |
2021-08-25 | target/mips: Replace GET_LMASK() macro by get_lmask(32) function | Philippe Mathieu-Daudé | 1 | -11/+21 |
2021-08-25 | target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers | Philippe Mathieu-Daudé | 1 | -22/+33 |
2021-08-25 | target/mips: Define gen_helper() macros in translate.h | Philippe Mathieu-Daudé | 2 | -12/+12 |
2021-08-25 | target/mips: Use tcg_constant_i32() in generate_exception_err() | Philippe Mathieu-Daudé | 1 | -5/+2 |
2021-08-25 | target/mips: Inline gen_helper_0e0i() | Philippe Mathieu-Daudé | 1 | -6/+2 |