riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-07-10	target/mips: enable GINVx support for I6400 and I6500	Marcin Nowakowski	1	-2/+2
2023-07-10	target/mips: Add support of two XBurst CPUs	Siarhei Volkau	1	-0/+46
2023-07-10	target/mips: Implement Loongson CSR instructions	Jiaxun Yang	1	-0/+9
2023-03-08	target/mips: Set correct CP0.Config[4, 5] values for M14K(c)	Marcin Nowakowski	1	-2/+8
2023-03-08	target/mips: Implement CP0.Config7.WII bit support	Marcin Nowakowski	1	-0/+3
2022-11-08	target/mips: Disable DSP ASE for Octeon68XX	Jiaxun Yang	1	-2/+2
2022-07-12	target/mips: introduce Cavium Octeon CPU model	Pavel Dovgalyuk	1	-0/+28
2021-11-02	target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU	Philippe Mathieu-Daudé	1	-1/+0
2021-11-02	target/mips: Fix Loongson-3A4000 MSAIR config register	Philippe Mathieu-Daudé	1	-0/+1
2021-08-25	target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr	Philippe Mathieu-Daudé	1	-1/+1
2021-08-25	target/mips: Document Loongson-3A CPU definitions	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips: Remove vendor specific CPU definitions	Philippe Mathieu-Daudé	1	-5/+7
2021-01-14	target/mips: Remove CPU_NANOMIPS32 definition	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips: Move msa_reset() to msa_helper.c	Philippe Mathieu-Daudé	1	-36/+0
2021-01-14	target/mips: Remove now unused ASE_MSA definition	Philippe Mathieu-Daudé	1	-4/+4
2021-01-14	target/mips: Simplify msa_reset()	Philippe Mathieu-Daudé	1	-0/+4
2021-01-14	target/mips: Rename translate_init.c as cpu-defs.c	Philippe Mathieu-Daudé	1	-0/+1007