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2018-06-15target-microblaze: Rework NOP/zero instruction handlingEdgar E. Iglesias1-11/+4
Remove the abort on a sequence of NOP/zero instructions. Always return early and avoid decoding NOP/zero instructions. This fixes Coverity CID 1391443. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-06-15target-microblaze: mmu: Correct masking of output addressesEdgar E. Iglesias1-1/+0
Correct the masking of output addresses. This fixes Coverity CID 1391441. Fixes: commit 3924a9aa02 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-3/+3
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-29target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias2-4/+6
Consolidate MMU enabled checks to cpu_mmu_index(). No functional changes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: cpu_mmu_index: Fixup indentationEdgar E. Iglesias1-7/+9
Fixup the indentation of cpu_mmu_index in preparation for future edits. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use tcg_gen_movcond in eval_cond_jmpEdgar E. Iglesias1-6/+10
Cleanup eval_cond_jmp to use tcg_gen_movcond_i64(). No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Convert env_btarget to i64Edgar E. Iglesias3-15/+25
Convert env_btarget to i64. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Remove argument b in eval_cc()Edgar E. Iglesias1-3/+3
Remove argument b in eval_cc() as it is always set to zero. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use table based condition-codes conversionEdgar E. Iglesias1-21/+20
Use a table based conversion to map condition-codes between MicroBlaze ISA encoding and TCG. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: mmu: Cleanup debug log messagesEdgar E. Iglesias1-20/+19
Cleanup debug log messages: * Avoid long 80+ character lines. * Remove D() macro and use qemu_log_mask. * Remove logs that are not very useful Suggested-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Simplify address computation using tcg_gen_addi_i32()Edgar E. Iglesias1-6/+1
Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Allow address sizes between 32 and 64 bitsEdgar E. Iglesias1-3/+2
Allow address sizes between 32 and 64 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Add support for extended access to TLBLOEdgar E. Iglesias5-18/+35
Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Plug a temp leakEdgar E. Iglesias1-4/+9
Plug a temp leak. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: mmu: Add a configurable output address maskEdgar E. Iglesias3-0/+3
Add a configurable output address mask, used to mimic the configurable physical address bit width. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: mmu: Prepare for 64-bit addressesEdgar E. Iglesias2-10/+10
Prepare for 64-bit addresses. This makes no functional difference as the upper parts of the 64-bit addresses are not yet reachable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: mmu: Remove unused register stateEdgar E. Iglesias2-3/+6
Add explicit handling for MMU_R_TLBX and log accesses to invalid MMU registers. We can now remove the state for all regs but PID, ZPR and TLBX (0 - 2). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: mmu: Add R_TBLX_MISS macrosEdgar E. Iglesias2-2/+7
Add a R_TBLX_MISS MASK and SHIFT macros. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Implement MFSE EAREdgar E. Iglesias1-1/+8
Implement MFSE EAR to enable access to the upper part of EAR. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Add Extended AddressingEdgar E. Iglesias3-13/+62
Add support for Extended Addressing. Load/stores with EA enabled concatenate two 32bit registers to form an extended address. We don't allow users to enable address sizes larger than 32 bits quite yet though. Once the MMU support is in, we'll turn it on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Setup for 64bit addressingEdgar E. Iglesias1-3/+3
Setup MicroBlaze builds for 64bit addressing. No functional change since the translator does not yet emit 64bit addresses. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Make special registers 64-bitEdgar E. Iglesias5-58/+70
Extend special registers to 64-bits. This is in preparation for MFSE/MTSE, moves to and from extended special registers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Fix MTS to FSREdgar E. Iglesias1-3/+1
Fix moves to FSR. Not only bit 31 is accessible. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Reuse more code when reg-decodingEdgar E. Iglesias1-29/+9
Reuse more code when decoding register numbers. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Use bool and extract32Edgar E. Iglesias1-6/+9
Use bool and extract32 to represent the to, clr and clrset flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Break out trap_illegal()Edgar E. Iglesias1-48/+27
Break out trap_illegal() to handle illegal operation traps. We now generally stop translation of the current insn if it's not valid. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Break out trap_userspace()Edgar E. Iglesias1-49/+27
Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Name special registers we supportEdgar E. Iglesias1-2/+2
Name special registers we support. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use TCGv for load/store addressesEdgar E. Iglesias4-42/+53
Use TCGv for load/store addresses, allowing for future computation of 64-bit load/store address. No functional change. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Remove pointer indirection for ld/st addressesEdgar E. Iglesias1-12/+12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Make compute_ldst_addr always use a tempEdgar E. Iglesias1-74/+37
Make compute_ldst_addr always use a temp. This simplifies the code a bit in preparation for adding support for 64bit addresses. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Bypass MMU with MMU_NOMMU_IDXEdgar E. Iglesias1-1/+2
Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Conditionalize setting of PVR11_USE_MMUEdgar E. Iglesias1-1/+2
Conditionalize setting of PVR11_USE_MMU on the use_mmu CPU property, otherwise we may incorrectly advertise an MMU via PVR when the core in fact has none. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Remove USE_MMU PVR checksEdgar E. Iglesias1-11/+1
We already have a CPU property to control if a core has an MMU or not. Remove USE_MMU PVR checks in favor of looking at the property. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Tighten up TCGv_i32 vs TCGv type usageEdgar E. Iglesias2-288/+295
Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Correct the PVR array sizeEdgar E. Iglesias1-1/+1
Correct the PVR array size, there are 13 PVR registers. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Correct special register array sizesEdgar E. Iglesias2-5/+4
Correct special register array sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Fallback to our latest CPU versionEdgar E. Iglesias1-2/+7
Today, when running QEMU in linux-user or with boards that don't select a specific CPU version, we treat it as an invalid version and log a message. Instead, if no specific version was selected, fallback to our latest CPU version. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: compute_ldst_addr: Use bool instead of intEdgar E. Iglesias1-5/+5
Use bool instead of int to represent flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_store: Use bool instead of unsigned intEdgar E. Iglesias1-3/+4
Use bool instead of unsigned int to represent flags. Also, use extract32 instead of open coding the bit extract. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_load: Use bool instead of unsigned intEdgar E. Iglesias1-3/+4
Use bool instead of unsigned int to represent flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-09target/microblaze: avoid integer overflow in next_page PC checkEmilio G. Cota1-3/+3
If the PC is in the last page of the address space, next_page_start overflows to 0. Fix it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-04-30target-microblaze: mmu: Make the TLBX MISS bit read-onlyEdgar E. Iglesias1-0/+4
Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: mmu: Make TLBSX write-onlyEdgar E. Iglesias1-1/+4
Make TLBSX write-only and guest-error log reads from it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Don't clobber the IMM reg for ld/st reversedEdgar E. Iglesias1-2/+0
Do not clobber the IMM register on reversed load/stores. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Fix trap checks for FPU insnsEdgar E. Iglesias1-1/+1
Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Respect MSR.PVR as read-onlyEdgar E. Iglesias1-1/+1
Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-1/+0
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée3-1/+3
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.1 at 2024-12-26 05:02:45 +0000