riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-04-30	target/microblaze: Add the div-zero-exception property	Edgar E. Iglesias	1	-2/+3
2019-06-10	target/microblaze: Use env_cpu, env_archcpu	Richard Henderson	1	-1/+1
2019-05-10	target/microblaze: Convert to CPUClass::tlb_fill	Richard Henderson	1	-19/+0
2019-01-22	target/microblaze: Switch to transaction_failed hook	Peter Maydell	1	-10/+12
2018-05-29	target-microblaze: Convert env_btarget to i64	Edgar E. Iglesias	1	-1/+1
2018-05-29	target-microblaze: Add support for extended access to TLBLO	Edgar E. Iglesias	1	-4/+4
2018-05-29	target-microblaze: Make special registers 64-bit	Edgar E. Iglesias	1	-4/+5
2018-05-29	target-microblaze: Use TCGv for load/store addresses	Edgar E. Iglesias	1	-4/+7
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	1	-0/+1
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-3/+3
2017-12-27	target/*helper: don't check retaddr before calling cpu_restore_state	Alex Bennée	1	-5/+2
2017-01-10	target-microblaze: Use clz opcode	Richard Henderson	1	-5/+0
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+523