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path: root/target/microblaze/helper.c
AgeCommit message (Expand)AuthorFilesLines
2020-09-01target/microblaze: Convert brk and brki to decodetreeRichard Henderson1-8/+2
2020-09-01target/microblaze: Use cc->do_unaligned_accessRichard Henderson1-0/+28
2020-09-01target/microblaze: Move bimm to BIMM_FLAGRichard Henderson1-1/+1
2020-09-01target/microblaze: Remove empty D macrosRichard Henderson1-7/+4
2020-09-01target/microblaze: Split out MSR[C] to its own variableRichard Henderson1-28/+30
2020-09-01target/microblaze: Fix width of ESRRichard Henderson1-1/+1
2020-09-01target/microblaze: Fix width of MSRRichard Henderson1-2/+2
2020-09-01target/microblaze: Fix width of PC and BTARGETRichard Henderson1-10/+6
2020-09-01target/microblaze: Split out BTR from env->sregsRichard Henderson1-2/+2
2020-09-01target/microblaze: Split out ESR from env->sregsRichard Henderson1-9/+9
2020-09-01target/microblaze: Split out EAR from env->sregsRichard Henderson1-3/+3
2020-09-01target/microblaze: Split out MSR from env->sregsRichard Henderson1-25/+24
2020-09-01target/microblaze: Split out PC from env->sregsRichard Henderson1-17/+17
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-6/+0
2019-05-10target/microblaze: Convert to CPUClass::tlb_fillRichard Henderson1-50/+57
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster1-1/+1
2018-05-29target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias1-3/+3
2018-05-29target-microblaze: Make special registers 64-bitEdgar E. Iglesias1-5/+10
2018-05-29target-microblaze: Bypass MMU with MMU_NOMMU_IDXEdgar E. Iglesias1-1/+2
2018-05-29target-microblaze: Remove USE_MMU PVR checksEdgar E. Iglesias1-11/+1
2018-05-29target-microblaze: Tighten up TCGv_i32 vs TCGv type usageEdgar E. Iglesias1-1/+1
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier1-2/+2
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+307