| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-10-30 | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ... | Peter Maydell | 2 | -48/+30 |
| 2017-10-27 | m68k: cleanup cpu type name composition | Igor Mammedov | 2 | -48/+30 |
| 2017-10-27 | Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging | Peter Maydell | 1 | -1/+1 |
| 2017-10-25 | disas: Remove unused flags arguments | Richard Henderson | 1 | -1/+1 |
| 2017-10-24 | tcg: Initialize cpu_env generically | Richard Henderson | 1 | -5/+0 |
| 2017-10-24 | tcg: define tcg_init_ctx and make tcg_ctx a pointer | Emilio G. Cota | 1 | -1/+1 |
| 2017-10-24 | target/m68k: check CF_PARALLEL instead of parallel_cpus | Emilio G. Cota | 3 | -15/+31 |
| 2017-10-24 | tcg: convert tb->cflags reads to tb_cflags(tb) | Emilio G. Cota | 1 | -3/+3 |
| 2017-10-24 | qom: Introduce CPUClass.tcg_initialize | Richard Henderson | 1 | -6/+1 |
| 2017-10-24 | tcg: Remove TCGV_EQUAL* | Richard Henderson | 1 | -1/+1 |
| 2017-10-09 | qom/cpu: move cpu_model null check to cpu_class_by_name() | Philippe Mathieu-Daudé | 1 | -4/+0 |
| 2017-09-10 | target/m68k: Switch fpu_rom from make_floatx80() to make_floatx80_init() | Kamil Rytarowski | 1 | -22/+22 |
| 2017-09-06 | target: [tcg] Use a generic enum for DISAS_ values | Lluís Vilanova | 1 | -1/+6 |
| 2017-09-01 | m68k: replace cpu_m68k_init() with cpu_generic_init() | Igor Mammedov | 3 | -22/+3 |
| 2017-07-31 | m68k/translate: fix incorrect copy/paste | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2017-07-19 | tcg: Pass generic CPUState to gen_intermediate_code() | Lluís Vilanova | 1 | -3/+2 |
| 2017-07-19 | target/m68k: optimize bcd_flags() using extract op | Philippe Mathieu-Daudé | 1 | -2/+1 |
| 2017-06-29 | target/m68k: add fmovem | Laurent Vivier | 3 | -30/+189 |
| 2017-06-29 | target/m68k: add explicit single and double precision operations (part 2) | Laurent Vivier | 3 | -8/+74 |
| 2017-06-29 | target/m68k: add fsglmul and fsgldiv | Laurent Vivier | 3 | -0/+36 |
| 2017-06-29 | target/m68k: add explicit single and double precision operations | Laurent Vivier | 3 | -5/+125 |
| 2017-06-29 | target/m68k: add fmovecr | Laurent Vivier | 3 | -1/+47 |
| 2017-06-29 | target/m68k: add fscc. | Laurent Vivier | 1 | -79/+131 |
| 2017-06-21 | target-m68k: add FPCR and FPSR | Laurent Vivier | 6 | -119/+421 |
| 2017-06-21 | target-m68k: define 96bit FP registers for gdb on 680x0 | Laurent Vivier | 1 | -0/+45 |
| 2017-06-21 | target-m68k: use floatx80 internally | Laurent Vivier | 7 | -291/+509 |
| 2017-06-21 | target-m68k: initialize FPU registers | Laurent Vivier | 1 | -1/+8 |
| 2017-06-21 | target-m68k: move fmove CR to a function | Laurent Vivier | 1 | -25/+31 |
| 2017-06-15 | target-m68k: define ext_opsize | Laurent Vivier | 1 | -19/+24 |
| 2017-06-15 | target-m68k: move FPU helpers to fpu_helper.c | Laurent Vivier | 3 | -89/+113 |
| 2017-06-15 | target/m68k: fix V flag for CC_OP_SUBx | Laurent Vivier | 1 | -1/+1 |
| 2017-06-07 | target/m68k: implement rtd | Laurent Vivier | 3 | -0/+14 |
| 2017-01-16 | Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-... | Peter Maydell | 2 | -2/+4 |
| 2017-01-14 | target-m68k: increment/decrement with SP | Laurent Vivier | 1 | -2/+12 |
| 2017-01-14 | target-m68k: CAS doesn't need aligned access | Laurent Vivier | 1 | -1/+0 |
| 2017-01-14 | target-m68k: manage pre-dec et post-inc in CAS | Laurent Vivier | 1 | -0/+9 |
| 2017-01-14 | target-m68k: fix gen_flush_flags() | Laurent Vivier | 1 | -1/+2 |
| 2017-01-14 | target-m68k: fix bit operation with immediate value | Laurent Vivier | 1 | -3/+10 |
| 2017-01-14 | target-m68k: Implement bfffo | Richard Henderson | 3 | -1/+62 |
| 2017-01-14 | target-m68k: Implement bitfield ops for memory | Richard Henderson | 4 | -2/+333 |
| 2017-01-14 | target-m68k: Implement bitfield ops for registers | Richard Henderson | 1 | -0/+210 |
| 2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée | 2 | -2/+4 |
| 2016-12-27 | target-m68k: free TCG variables that are not | Laurent Vivier | 1 | -9/+32 |
| 2016-12-27 | target-m68k: add rol/ror/roxl/roxr instructions | Laurent Vivier | 1 | -0/+391 |
| 2016-12-27 | target-m68k: Inline shifts | Richard Henderson | 3 | -80/+201 |
| 2016-12-27 | target-m68k: Do not cpu_abort on undefined insns | Richard Henderson | 1 | -3/+5 |
| 2016-12-27 | target-m68k: Implement 680x0 movem | Laurent Vivier | 1 | -23/+107 |
| 2016-12-27 | target-m68k: add cas/cas2 ops | Laurent Vivier | 3 | -0/+265 |
| 2016-12-27 | target-m68k: add abcd/sbcd/nbcd | Laurent Vivier | 1 | -0/+220 |
| 2016-12-27 | target-m68k: add 680x0 divu/divs variants | Laurent Vivier | 5 | -70/+211 |
