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AgeCommit message (Expand)AuthorFilesLines
2017-01-16Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-...Peter Maydell2-2/+4
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier1-2/+12
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier1-1/+0
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier1-0/+9
2017-01-14target-m68k: fix gen_flush_flags()Laurent Vivier1-1/+2
2017-01-14target-m68k: fix bit operation with immediate valueLaurent Vivier1-3/+10
2017-01-14target-m68k: Implement bfffoRichard Henderson3-1/+62
2017-01-14target-m68k: Implement bitfield ops for memoryRichard Henderson4-2/+333
2017-01-14target-m68k: Implement bitfield ops for registersRichard Henderson1-0/+210
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-2/+4
2016-12-27target-m68k: free TCG variables that are notLaurent Vivier1-9/+32
2016-12-27target-m68k: add rol/ror/roxl/roxr instructionsLaurent Vivier1-0/+391
2016-12-27target-m68k: Inline shiftsRichard Henderson3-80/+201
2016-12-27target-m68k: Do not cpu_abort on undefined insnsRichard Henderson1-3/+5
2016-12-27target-m68k: Implement 680x0 movemLaurent Vivier1-23/+107
2016-12-27target-m68k: add cas/cas2 opsLaurent Vivier3-0/+265
2016-12-27target-m68k: add abcd/sbcd/nbcdLaurent Vivier1-0/+220
2016-12-27target-m68k: add 680x0 divu/divs variantsLaurent Vivier5-70/+211
2016-12-27target-m68k: add 64bit mullLaurent Vivier1-12/+50
2016-12-27target-m68k: add cmpmLaurent Vivier1-0/+16
2016-12-27target-m68k: Split gen_lea and gen_eaRichard Henderson1-53/+59
2016-12-27target-m68k: Delay autoinc writebackRichard Henderson1-20/+64
2016-12-20Move target-* CPU file into a target/ folderThomas Huth11-0/+5921
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