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2017-10-27m68k: cleanup cpu type name compositionIgor Mammedov2-48/+30
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-5/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/m68k: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota3-15/+31
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+1
2017-10-24tcg: Remove TCGV_EQUAL*Richard Henderson1-1/+1
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-4/+0
2017-09-10target/m68k: Switch fpu_rom from make_floatx80() to make_floatx80_init()Kamil Rytarowski1-22/+22
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-1/+6
2017-09-01m68k: replace cpu_m68k_init() with cpu_generic_init()Igor Mammedov3-22/+3
2017-07-31m68k/translate: fix incorrect copy/pastePhilippe Mathieu-Daudé1-1/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-19target/m68k: optimize bcd_flags() using extract opPhilippe Mathieu-Daudé1-2/+1
2017-06-29target/m68k: add fmovemLaurent Vivier3-30/+189
2017-06-29target/m68k: add explicit single and double precision operations (part 2)Laurent Vivier3-8/+74
2017-06-29target/m68k: add fsglmul and fsgldivLaurent Vivier3-0/+36
2017-06-29target/m68k: add explicit single and double precision operationsLaurent Vivier3-5/+125
2017-06-29target/m68k: add fmovecrLaurent Vivier3-1/+47
2017-06-29target/m68k: add fscc.Laurent Vivier1-79/+131
2017-06-21target-m68k: add FPCR and FPSRLaurent Vivier6-119/+421
2017-06-21target-m68k: define 96bit FP registers for gdb on 680x0Laurent Vivier1-0/+45
2017-06-21target-m68k: use floatx80 internallyLaurent Vivier7-291/+509
2017-06-21target-m68k: initialize FPU registersLaurent Vivier1-1/+8
2017-06-21target-m68k: move fmove CR to a functionLaurent Vivier1-25/+31
2017-06-15target-m68k: define ext_opsizeLaurent Vivier1-19/+24
2017-06-15target-m68k: move FPU helpers to fpu_helper.cLaurent Vivier3-89/+113
2017-06-15target/m68k: fix V flag for CC_OP_SUBxLaurent Vivier1-1/+1
2017-06-07target/m68k: implement rtdLaurent Vivier3-0/+14
2017-01-16Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-...Peter Maydell2-2/+4
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier1-2/+12
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier1-1/+0
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier1-0/+9
2017-01-14target-m68k: fix gen_flush_flags()Laurent Vivier1-1/+2
2017-01-14target-m68k: fix bit operation with immediate valueLaurent Vivier1-3/+10
2017-01-14target-m68k: Implement bfffoRichard Henderson3-1/+62
2017-01-14target-m68k: Implement bitfield ops for memoryRichard Henderson4-2/+333
2017-01-14target-m68k: Implement bitfield ops for registersRichard Henderson1-0/+210
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-2/+4
2016-12-27target-m68k: free TCG variables that are notLaurent Vivier1-9/+32
2016-12-27target-m68k: add rol/ror/roxl/roxr instructionsLaurent Vivier1-0/+391
2016-12-27target-m68k: Inline shiftsRichard Henderson3-80/+201
2016-12-27target-m68k: Do not cpu_abort on undefined insnsRichard Henderson1-3/+5
2016-12-27target-m68k: Implement 680x0 movemLaurent Vivier1-23/+107
2016-12-27target-m68k: add cas/cas2 opsLaurent Vivier3-0/+265
2016-12-27target-m68k: add abcd/sbcd/nbcdLaurent Vivier1-0/+220
2016-12-27target-m68k: add 680x0 divu/divs variantsLaurent Vivier5-70/+211
2016-12-27target-m68k: add 64bit mullLaurent Vivier1-12/+50
2016-12-27target-m68k: add cmpmLaurent Vivier1-0/+16
2016-12-27target-m68k: Split gen_lea and gen_eaRichard Henderson1-53/+59
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