aboutsummaryrefslogtreecommitdiff
path: root/target/loongarch
AgeCommit message (Collapse)AuthorFilesLines
3 daystarget/loongarch: Fix valid virtual address checkingBibo Mao1-2/+2
On LoongArch64 system, the high 32 bit of 64 bit virtual address should be 0x00000[0-7]yyy or 0xffff8yyy. The bit from 47 to 63 should be all 0 or all 1. Function get_physical_address() only checks bit 48 to 63, there will be problem with the following test case. On physical machine, there is bus error report and program exits abnormally. However on qemu TCG system emulation mode, the program runs normally. The virtual address 0xffff000000000000ULL + addr and addr are treated the same on TLB entry checking. This patch fixes this issue. void main() { void *addr, *addr1; int val; addr = malloc(100); *(int *)addr = 1; addr1 = 0xffff000000000000ULL + addr; val = *(int *)addr1; printf("val %d \n", val); } Cc: qemu-stable@nongnu.org Signed-off-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-ID: <20250714015446.746163-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-07-15target/qmp: Use target_cpu_type()Philippe Mathieu-Daudé1-1/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20250708215320.70426-2-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-07-11target/loongarch: Remove unnecessary page size validity checkingBibo Mao1-17/+10
Page size of TLB entry comes from CSR STLBPS and pwcl register. With huge page, it is dir_base + dir_width from pwcl register. With normal page, it is field of PTBASE from pwcl register. So it is ok to check validity in function helper_ldpte() and function helper_csrwr_stlbps(). And it is unnecessary in tlb entry fill path. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-11target/loongarch: Fix CSR STLBPS register write emulationBibo Mao1-0/+4
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register write operation. However there is only parameter checking action, and no register updating action. Here update value of CSR_STLBPS when parameter passes to check. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-11target/loongarch: Correct spelling in helper_csrwr_pwcl()Bibo Mao1-2/+2
There is small typo issue in function helper_csrwr_pwcl(), this patch corrects this issue. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-02treewide: fix paths for relocated files in commentsSean Wei1-1/+1
After the docs directory restructuring, several comments refer to paths that no longer exist. Replace these references to the current file locations so readers can find the correct files. Related commits --------------- 189c099f75f (Jul 2021) docs: collect the disparate device emulation docs into one section Rename docs/system/{ => devices}/nvme.rst 5f4c96b779f (Feb 2023) docs/system/loongarch: update loongson3.rst and rename it to virt.rst Rename docs/system/loongarch/{loongson3.rst => virt.rst} fe0007f3c1d (Sep 2023) exec: Rename cpu.c -> cpu-target.c Rename cpus-common.c => cpu-common.c 42fa9665e59 (Apr 2025) exec: Restrict 'cpu_ldst.h' to accel/tcg/ Rename include/{exec/cpu_ldst.h => accel/tcg/cpu-ldst.h} Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <20250616.qemu.relocated.06@sean.taipei> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-06-19target/loongarch: fix vldi/xvldi raise wrong errorSong Gao1-2/+11
on qemu we got an aborted error ** ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value: code should not be reached Bail out! ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value: code should not be reached Aborted (core dumped) but on 3A600/3A5000 we got a "Illegal instruction" error. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971 Fixes: 29bb5d727ff ("target/loongarch: Implement vldi") Cc: qemu-stable@nongnu.org Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/loongarch/virt: Add kernel irqchip supportBibo Mao2-0/+17
If kvm_irqchip_in_kernel() return true, interrupt controller ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And it is not necessary to create memory region for these devices in user space. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063607.2557540-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19target/loongarch: Report error with split kernel_irqchip optionBibo Mao1-1/+6
Option kernel_irqchip=split is not supported on LoongArch virt machine, report error and exit if detect split kernel_irqchip option. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063431.2557468-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-10target/loongarch: add check for fcondSong Gao2-11/+30
fcond only has 22 types, add a check for fcond. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2972 Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250603024810.350510-1-gaosong@loongson.cn>
2025-05-30Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi1-0/+4
* target/i386/kvm: Intel TDX support * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz # ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x # Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 # A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW # BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ # Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== # =XmkU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 May 2025 03:05:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) target/i386/tcg/helper-tcg: fix file references in comments target/i386: Add support for EPYC-Turin model target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits rust: make declaration of dependent crates more consistent docs: Add TDX documentation i386/tdx: Validate phys_bits against host value i386/tdx: Make invtsc default on i386/tdx: Don't treat SYSCALL as unavailable i386/tdx: Fetch and validate CPUID of TD guest target/i386: Print CPUID subleaf info for unsupported feature i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386/cgs: Introduce x86_confidential_guest_check_features() i386/tdx: Define supported KVM features for TDX i386/tdx: Add XFD to supported bit of TDX i386/tdx: Add supported CPUID bits relates to XFAM i386/tdx: Add supported CPUID bits related to TD Attributes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-29Merge tag 'pull-qapi-2025-05-28' of https://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi1-1/+1
QAPI patches patches for 2025-05-28 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmg3UTYSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTz9cQALqbici35rI19BYR8XNTcIK1sS6iB9wx # 6vLLix7a+/vsmBXiHEfo6nnlTBsU1NVP+8Tvx8+6TRBUnjK+9YaPZHE8k6lGglWm # 5lbue7nUlzaF4TfTmqrsCeeYKvc8iwC5TUBHbsLNpf9IIvNHbRm4IrD4ySnur+mN # vTQWEvLkT9quh5KPaiZajlQulIpaFZjwREJ2U8LC6Tb+t0qtAGL6hc+etI49re6A # 2jJq29G+hSxK87FBFwgilh4Dl5DCDAe75Plp1Opy0wyowM06ilSATYBJ6SL4B3wg # RKQXmHiHZCxk+MLs3vhE65bhNmMLkf+xbY/jxSNs5Hisj4Snt7bLqWRaBAhkRZOz # ZCyGMI6lpJELo8VIEE2gB8m/kf6YAG4pfLdZkIZCuFyW2I6b3OQjOn5G0td6JtvX # a5ygtuzi8VIxA3FcODb/EMNAPOv6B4aHgW3IaiwLB2kgeiqR+yMIE6zqZZHrEGUl # A/S7an99vbHgSFPtJ37VaUEdDnb06b4ebIvNyBzrgtXO8ekHaXAjCh52UYkLFOJe # S0dBrENj6M1yJ8HPwqWgP25PdlBAbCGHCsaZScrv7j08Q7sNJbQz0mmrCi0V/djV # riZBVcODabQ9mveMc1KJplKwIg351YJk3XwHqMLKHw9srMl3z3YcZf6T3e/G3ScQ # rlqRDslZvvgd # =3NrB # -----END PGP SIGNATURE----- # gpg: Signature made Wed 28 May 2025 14:08:54 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2025-05-28' of https://repo.or.cz/qemu/armbru: qapi: use imperative style in documentation qapi: make all generated files common qapi: remove qapi_specific_outputs from meson.build qapi: make s390x specific CPU commands unconditionally available qapi: make most CPU commands unconditionally available qapi: Make CpuModelExpansionInfo::deprecated-props optional and generic qapi: remove the misc-target.json file qapi: make Xen event commands unconditionally available qapi: make SGX commands unconditionally available qapi: expose query-gic-capability command unconditionally qapi: make SEV commands unconditionally available qapi: expand docs for SEV commands qapi: expose rtc-reset-reinjection command unconditionally Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-28kvm: Introduce kvm_arch_pre_create_vcpu()Xiaoyao Li1-0/+4
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent work prior to create any vcpu. This is for i386 TDX because it needs call TDX_INIT_VM before creating any vcpu. The specific implementation for i386 will be added in the future patch. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-8-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28qapi: make most CPU commands unconditionally availableDaniel P. Berrangé1-1/+1
This removes the TARGET_* conditions from all the CPU commands that are conceptually target independent. Top level stubs are provided to cope with targets which do not currently implement all of the commands. Adjust the doc comments accordingly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-10-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28target/loongarch: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check va32 state. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOpsRichard Henderson1-1/+2
Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_stateRichard Henderson1-10/+12
Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.hRichard Henderson2-14/+13
For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Introduce TCGCPUOps.cpu_exec_resetRichard Henderson1-0/+1
Initialize all instances with cpu_reset(), so that there is no functional change. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30include: Remove 'exec/exec-all.h'Philippe Mathieu-Daudé6-6/+0
"exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-14-philmd@linaro.org>
2025-04-25qom: Have class_init() take a const data argumentPhilippe Mathieu-Daudé1-3/+3
Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>
2025-04-24Merge tag 'pull-loongarch-20250424' of https://github.com/gaosong715/qemu ↵Stefan Hajnoczi11-907/+929
into staging pull-loongarch-20230424 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCaAmmRQAKCRBAov/yOSY+ # 3yZoA/4udi9ZmLsaiPqfKCS+0eF8XScIT493lVD359lFTBTT7mshh9PPhTLzdtiC # 8fcfYi7jSjfC9gGTjPgnNCOzKIg3Gbdl61AFDgIwd8q/5HQAgonHAywTUtmqDaPK # bXZ/JkkJQby2dla6015XKQS/d/EXWHgYjrcb1JZIRoaLworZPw== # =zBCJ # -----END PGP SIGNATURE----- # gpg: Signature made Wed 23 Apr 2025 22:47:33 EDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20250424' of https://github.com/gaosong715/qemu: target/loongarch: Guard BCEQZ/BCNEZ instructions with FP feature target/loongarch: Add CRC feature flag and use it to gate CRC instructions linux-user/loongarch64: Decode BRK break codes for FPE signals target/loongarch: Move definition of TCG specified function to tcg directory target/loongarch: Add static definition with function loongarch_tlb_search() target/loongarch: Move function loongarch_tlb_search to directory tcg target/loongarch: Define function loongarch_get_addr_from_tlb() non-static target/loongarch: Set function loongarch_map_address() with common code target/loongarch: Add stub function loongarch_get_addr_from_tlb target/loongarch: Move function get_dir_base_width to common directory target/loongarch: Add function loongarch_get_addr_from_tlb target/loongarch: Move header file helper.h to directory tcg hw/intc/loongarch_pch_msi: Remove gpio input handler Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-24target/loongarch: Guard BCEQZ/BCNEZ instructions with FP featureWANG Rui1-2/+2
The BCEQZ and BCNEZ instructions depend on access to condition codes from floating-point comparisons. Previously, these instructions were unconditionally enabled for 64-bit targets. This patch updates their translation to be gated under the `FP` feature flag instead, ensuring they are only available when the floating-point unit is present. This improves correctness for CPUs lacking floating-point support. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20250418082103.447780-3-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add CRC feature flag and use it to gate CRC instructionsWANG Rui4-11/+12
This patch replaces the obsolete IOCSR_BRD bit with CRC in cpucfg1[25], in both LA464 and LA132 CPU initialization functions. The corresponding field macro in `cpu.h` is updated to reflect this change. Additionally, the availability macro `avail_CRC()` is introduced in `translate.h` to check the CRC feature flag. All CRC-related instruction translations are updated to be gated by the new CRC feature flag instead of hardcoded CPU features. This ensures correctness and configurability when enabling CRC instructions based on hardware capabilities. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250418082103.447780-2-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move definition of TCG specified function to tcg directoryBibo Mao3-5/+5
Function loongarch_cpu_tlb_fill() only works in TCG mode, move its definition from header file internals.h to file tcg/tcg_loongarch.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-10-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add static definition with function loongarch_tlb_search()Bibo Mao2-4/+2
Function loongarch_tlb_search() is only referenced in file tcg/tlb_helper.c, define this function with static attribution. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-9-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move function loongarch_tlb_search to directory tcgBibo Mao2-146/+145
Function loongarch_tlb_search() and loongarch_map_tlb_entry() works only in TCG mode, move these functions to directory tcg. There is no any function change, only code moving. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-8-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Define function loongarch_get_addr_from_tlb() non-staticBibo Mao2-8/+7
Define function loongarch_get_addr_from_tlb() non-static, and add its definition in header file tcg/tcg_loongarch.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-7-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Set function loongarch_map_address() with common codeBibo Mao1-10/+0
Function loongarch_map_address is to get physical address from virtual address, it is used by qmp commands to dump memory from virtual address. It is used by kvm mode also, here move function loongarch_map_address() out of macro CONFIG_TCG. And it is common code, the similar with function loongarch_page_table_walker(). Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-6-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add stub function loongarch_get_addr_from_tlbBibo Mao1-0/+9
Stub function loongarch_get_addr_from_tlb() is added if option CONFIG_TCG is not enabled, so this function can be called in KVM only mode. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move function get_dir_base_width to common directoryBibo Mao2-28/+28
Function get_dir_base_width() is used by loongarch_page_table_walker(), so it is used by KVM mode also, here move this function from directory tcg to common directory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add function loongarch_get_addr_from_tlbBibo Mao1-6/+26
Function loongarch_get_addr_from_tlb() is added to get physical address from TLB tables. TLB table only works in TCG mode, in future this function will be moved to TCG directory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move header file helper.h to directory tcgBibo Mao2-718/+724
Header file helper.h is specified for tcg mode, move this file to directory tcg. And create new file helper.h to include header file in tcg mode. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-23tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported fieldPhilippe Mathieu-Daudé1-0/+1
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250405161320.76854-17-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23tcg: Remove the TCG_GUEST_DEFAULT_MO definition globallyPhilippe Mathieu-Daudé2-3/+1
By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23tcg: Define guest_default_memory_order in TCGCPUOpsPhilippe Mathieu-Daudé1-0/+2
Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23exec: Restrict 'cpu_ldst.h' to accel/tcg/Philippe Mathieu-Daudé6-6/+6
Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23tcg: Always define TARGET_INSN_START_EXTRA_WORDSPhilippe Mathieu-Daudé1-0/+2
Do not define TARGET_INSN_START_EXTRA_WORDS under the hood, have each target explicitly define it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23exec/cpu-all: remove this headerPierrick Bouvier1-2/+0
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-16-pierrick.bouvier@linaro.org>
2025-04-23exec/cpu-all: transfer exec/cpu-common include to cpu.h headersPierrick Bouvier1-0/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-15-pierrick.bouvier@linaro.org>
2025-04-23exec/cpu-all: remove exec/target_page includePierrick Bouvier3-0/+3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23exec/cpu-all: remove exec/cpu-interrupt includePierrick Bouvier1-0/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-8-pierrick.bouvier@linaro.org>
2025-04-23target/loongarch: Restrict SoftMMU mmu_index() to TCGPhilippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250401080938.32278-11-philmd@linaro.org>
2025-04-23include/system: Move exec/address-spaces.h to system/address-spaces.hRichard Henderson1-1/+1
Convert the existing includes with sed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/system: Move exec/memory.h to system/memory.hRichard Henderson1-1/+1
Convert the existing includes with sed -i ,exec/memory.h,system/memory.h,g Move the include within cpu-all.h into a !CONFIG_USER_ONLY block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/exec: Split out accel/tcg/cpu-mmu-index.hRichard Henderson1-0/+1
The implementation of cpu_mmu_index was split between cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the plumbing common to user and system mode. Using MMU_USER_IDX requires the cpu.h for a specific target, and so is restricted to when we're compiling per-target. Include the new header only where needed. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-27target/loongarch: Fix the cpu unplug resource leakXianglai Li2-1/+7
When the cpu is created, qemu_add_vm_change_state_handler is called in the kvm_arch_init_vcpu function to create the VMChangeStateEntry resource. However, the resource is not released when the cpu is destroyed. This results in a qemu process segment error when the virtual machine restarts after the cpu is unplugged. This patch solves the problem by adding the corresponding resource release process to the kvm_arch_destroy_vcpu function. Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20250324123328.518076-1-lixianglai@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-03-23Merge tag 'pull-error-2025-03-21' of https://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi2-5/+8
Error reporting patches for 2025-03-21 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmfdeWkSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTeigQAJicOKRQPm5qCn/XP70k6OuvTXsU8Fw/ # FVXE3I1lE9MnUDVHe9RgY79piS7oQ/pR92QcPxTx/Kj22gSiFBgrH5q0bURZAOxR # /85DTxjVGuz3pAMhfXZ3rRyJGhX4MgPmYYXkvOyrz0cpHMR3DN9helIfdVfVtWAh # VTVEH2PKdd9I56gbi9irlfdeh/+Nb2+1swBbtpUWFthDPj7Cib+gHsrJQbRX7qSf # 0eEGVgqydfAuSLbMnD6SwCXbuJQ/mHg5+71QmSJFqthRzLHqXuUk6m6n8EXTgE6D # MEdwkhSZ6ksNEWkzBvv3lfO8WnAqH0jp+xkuDTJabJzZG17pC61B2HQRsrFxZxqU # Ftr4XDPccDc9ohX0GYwCpvfW2Y8ZLzjurc04dpSPoqIBZxAPySirWOmTbT7I6MFF # EVt4VdjwXi0jSLWeH0yq6NmpSiKDxC6kY78xvAx6Pr9QQWtCeH/sQKXQ+16IqqTf # aeM4zXUs8cWD+QULqkxp7aHJPg91zU+BQGopkmMCpCNGwnzJPajfJgCDsWHnn47z # jiuOISWS650bUL6D4GgC1l2pYVPqt3ybF6DZL0giDE6NPpIich/KA1SSVXDy3bVK # AGRMczC40GHvlDFKkLI0j5HM1HY8aYdn44skY28R/+SzyV0463u5oljcYmDe7oWC # iLtinF/DKCDa # =FJPm # -----END PGP SIGNATURE----- # gpg: Signature made Fri 21 Mar 2025 10:36:25 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-error-2025-03-21' of https://repo.or.cz/qemu/armbru: target/loongarch: Clean up virt_cpu_irq_init() error handling target/loongarch: Remove unnecessary temporary variable assignment hw/loongarch/virt: Eliminate error_propagate() target/loongarch: Fix error handling of KVM feature checks hw/xen: Downgrade a xen_bus_realize() non-error to warning hw/xen: Fix xen_bus_realize() error handling error: Strip trailing '\n' from an error string argument cryptodev: Fix error handling in cryptodev_lkcf_execute_task() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-21target/loongarch: fix bad shift in check_ps()Song Gao3-7/+7
In expression 1ULL << tlb_ps, left shifting by more than 63 bits has undefined behavior. The shift amount, tlb_ps, is as much as 64. check "tlb_ps >=64" to fix. Resolves: Coverity CID 1593475 Fixes: d882c284a3 ("target/loongarch: check tlb_ps") Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-20target/loongarch: Remove unnecessary temporary variable assignmentBibo Mao1-3/+2
Temporary variable ret is assigned at last line and return, it can be removed and return directly. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250320032158.1762751-6-maobibo@loongson.cn> Signed-off-by: Markus Armbruster <armbru@redhat.com>
generated by cgit v1.1 at 2025-08-03 12:06:27 +0000