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AgeCommit message (Expand)AuthorFilesLines
2023-06-16target/loongarch: Fix CSR.DMW0-3.VSEG checkJiajie Chen1-2/+2
2023-06-16hw/intc: Set physical cpuid route for LoongArch ipi deviceTianrui Zhao1-0/+2
2023-06-05target/*: Add missing includes of exec/translation-block.hRichard Henderson1-2/+1
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson3-8/+2
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+4
2023-05-26target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system core...Song Gao1-13/+26
2023-05-26target/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADVSong Gao2-3/+5
2023-05-11target/loongarch: Do not include tcg-ldst.hRichard Henderson2-2/+0
2023-05-10target/loongarch: Terminate vmstate subsections listRichard Henderson1-0/+1
2023-05-06target/loongarch: CPUCFG support LSXSong Gao1-0/+1
2023-05-06target/loongarch: Use {set/get}_gpr replace to cpu_fprSong Gao5-43/+129
2023-05-06target/loongarch: Implement vldiSong Gao3-0/+148
2023-05-06target/loongarch: Implement vld vstSong Gao4-0/+239
2023-05-06target/loongarch: Implement vilvl vilvh vextrins vshufSong Gao5-0/+248
2023-05-06target/loongarch: Implement vreplve vpack vpickSong Gao5-0/+319
2023-05-06target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vrSong Gao3-0/+173
2023-05-06target/loongarch: Implement vbitsel vsetSong Gao5-0/+174
2023-05-06target/loongarch: Implement vfcmpSong Gao5-0/+190
2023-05-06target/loongarch: Implement vseq vsle vsltSong Gao5-0/+332
2023-05-06target/loongarch: Implement LSX fpu fcvt instructionsSong Gao5-0/+600
2023-05-06target/loongarch: Implement LSX fpu arith instructionsSong Gao8-1/+377
2023-05-06target/loongarch: Implement vfrstpSong Gao5-0/+61
2023-05-06target/loongarch: Implement vbitclr vbitset vbitrevSong Gao5-0/+437
2023-05-06target/loongarch: Implement vpcntSong Gao5-0/+38
2023-05-06target/loongarch: Implement vclo vclzSong Gao5-0/+67
2023-05-06target/loongarch: Implement vssrlrn vssrarnSong Gao5-0/+478
2023-05-06target/loongarch: Implement vssrln vssranSong Gao5-0/+499
2023-05-06target/loongarch: Implement vsrlrn vsrarnSong Gao5-0/+190
2023-05-06target/loongarch: Implement vsrln vsranSong Gao5-0/+179
2023-05-06target/loongarch: Implement vsrlr vsrarSong Gao5-0/+176
2023-05-06target/loongarch: Implement vsllwil vextlSong Gao5-0/+89
2023-05-06target/loongarch: Implement vsll vsrl vsra vrotrSong Gao3-0/+108
2023-05-06target/loongarch: Implement LSX logic instructionsSong Gao5-0/+94
2023-05-06target/loongarch: Implement vmskltz/vmskgez/vmsknzSong Gao5-0/+141
2023-05-06target/loongarch: Implement vsigncovSong Gao5-0/+75
2023-05-06target/loongarch: Implement vexthSong Gao5-0/+82
2023-05-06target/loongarch: Implement vsatSong Gao5-0/+168
2023-05-06target/loongarch: Implement vdiv/vmodSong Gao5-0/+105
2023-05-06target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}Song Gao5-0/+817
2023-05-06target/loongarch: Implement vmul/vmuh/vmulw{ev/od}Song Gao5-0/+732
2023-05-06target/loongarch: Implement vmax/vminSong Gao5-0/+319
2023-05-06target/loongarch: Implement vaddaSong Gao5-0/+87
2023-05-06target/loongarch: Implement vabsdSong Gao5-0/+133
2023-05-06target/loongarch: Implement vavg/vavgrSong Gao5-0/+281
2023-05-06target/loongarch: Implement vaddw/vsubwSong Gao5-0/+1116
2023-05-06target/loongarch: Implement vhaddw/vhsubwSong Gao5-0/+150
2023-05-06target/loongarch: Implement vsadd/vssubSong Gao3-0/+51
2023-05-06target/loongarch: Implement vnegSong Gao3-0/+37
2023-05-06target/loongarch: Implement vaddi/vsubiSong Gao3-0/+62
2023-05-06target/loongarch: Implement vadd/vsubSong Gao5-0/+139
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