aboutsummaryrefslogtreecommitdiff
path: root/target/loongarch/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2023-05-06target/loongarch: Implement LSX fpu arith instructionsSong Gao1-0/+4
2023-05-06target/loongarch: Add CHECK_SXE maccro for check LSX enableSong Gao1-0/+2
2023-05-06target/loongarch: Add LSX data type VRegSong Gao1-1/+20
2023-03-03target/loongarch: Implement Chip Configuraiton Version Register(0x0000)Song Gao1-0/+1
2023-02-27target/loongarch/cpu: Restrict "memory.h" header to sysemuPhilippe Mathieu-Daudé1-0/+2
2023-02-27target/loongarch/cpu: Remove unused "sysbus.h" headerBernhard Beschow1-1/+0
2022-12-16target/loongarch: Convert to 3-phase resetPeter Maydell1-2/+2
2022-11-07target/loongarch: Separate the hardware flags into MMU index and PLVRui Wang1-9/+9
2022-11-04target/loongarch: Fix emulation of float-point disable exceptionRui Wang1-0/+2
2022-11-04target/loongarch: Adjust the layout of hardware flags bit fieldsRui Wang1-1/+8
2022-11-04target/loongarch: Add exception subcodeSong Gao1-27/+31
2022-08-05target/loongarch: Fix macros SET_FPU_* in cpu.hQi Hu1-3/+15
2022-07-19hw/loongarch: Add fdt supportXiaojuan Yang1-0/+3
2022-07-04target/loongarch: Adjust functions and structure to support user-modeSong Gao1-0/+6
2022-07-04target/loongarch: remove badaddr from CPULoongArchSong Gao1-2/+0
2022-06-06hw/loongarch: Add LoongArch load elf function.Xiaojuan Yang1-0/+2
2022-06-06target/loongarch: Add LoongArch IOCSR instructionXiaojuan Yang1-0/+25
2022-06-06target/loongarch: Add constant timer supportXiaojuan Yang1-0/+4
2022-06-06target/loongarch: Add LoongArch interrupt and exception handleXiaojuan Yang1-0/+2
2022-06-06target/loongarch: Add MMU support for LoongArch CPU.Xiaojuan Yang1-0/+51
2022-06-06target/loongarch: Add CSRs definitionXiaojuan Yang1-0/+64
2022-06-06target/loongarch: Add core definitionSong Gao1-0/+243
generated by cgit v1.1 at 2025-01-16 08:40:24 +0000