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AgeCommit message (Expand)AuthorFilesLines
2023-09-26target/i386/svm_helper: eliminate duplicate local variablePaolo Bonzini1-2/+0
2023-09-26target/i386/seg_helper: remove shadowed variablePaolo Bonzini1-12/+10
2023-09-26target/i386/seg_helper: introduce tss_set_busyPaolo Bonzini1-14/+17
2023-09-26target/i386/translate: avoid shadowed local variablesPaolo Bonzini1-3/+1
2023-09-20i386: spelling fixesMichael Tokarev1-4/+4
2023-09-07Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi5-12/+54
2023-09-01target/i386: fix memory operand size for CVTPS2PDPaolo Bonzini2-7/+37
2023-09-01target/i386: generalize operand size "ph" for use in CVTPS2PDPaolo Bonzini2-4/+4
2023-09-01target/i386: raise FERR interrupt with iothread lockedPaolo Bonzini2-1/+13
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2-0/+2
2023-08-04target/i386: Check CR0.TS before enter_mmxMatt Borgerson1-4/+6
2023-06-29target/i386: emulate 64-bit ring 0 for linux-user if LM feature is setPaolo Bonzini1-2/+4
2023-06-26target/i386: implement SYSCALL/SYSRET in 32-bit emulatorsPaolo Bonzini4-9/+9
2023-06-26target/i386: implement RDPID in TCGPaolo Bonzini2-11/+34
2023-06-26target/i386: sysret and sysexit are privilegedPaolo Bonzini1-2/+2
2023-06-26target/i386: AMD only supports SYSENTER/SYSEXIT in 32-bit modePaolo Bonzini1-4/+6
2023-06-26target/i386: Intel only supports SYSCALL/SYSRET in long modePaolo Bonzini1-1/+8
2023-06-26target/i386: TCG supports WBNOINVDPaolo Bonzini1-1/+1
2023-06-26target/i386: do not accept RDSEED if CPUID bit absentPaolo Bonzini1-0/+8
2023-06-26target/i386: fix INVD vmexitPaolo Bonzini1-1/+1
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-1/+1
2023-06-20meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé1-1/+1
2023-06-20target/i386: Simplify i386_tr_init_disas_context()Philippe Mathieu-Daudé1-3/+0
2023-06-13target/i386: Rename helper template headers as '.h.inc'Philippe Mathieu-Daudé5-8/+531
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-42/+10
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+5
2023-05-18target/i386: Fix exception classes for MOVNTPS/MOVNTPD.Ricky Zhou1-2/+3
2023-05-18target/i386: Fix exception classes for SSE/AVX instructions.Ricky Zhou1-23/+23
2023-05-18target/i386: Fix and add some comments next to SSE/AVX instructions.Ricky Zhou1-12/+12
2023-05-18target/i386: fix avx2 instructions vzeroall and vpermdqXinyu Li1-1/+1
2023-05-18target/i386: fix operand size for VCOMI/VUCOMI instructionsPaolo Bonzini1-2/+13
2023-04-23tcg: Replace tcg_abort with g_assert_not_reachedRichard Henderson1-10/+10
2023-04-20target/i386: Avoid unreachable variable declaration in mmu_translate()Peter Maydell1-1/+1
2023-03-13target/i386: Avoid use of tcg_const_* throughoutRichard Henderson1-41/+42
2023-03-05target/i386: Simplify POPFRichard Henderson1-44/+11
2023-03-05target/i386: Drop tcg_temp_freeRichard Henderson3-62/+0
2023-03-01target/i386: Don't use tcg_temp_local_newRichard Henderson1-18/+9
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2023-03-01target/i386: Replace `tb_pc()` with `tb->pc`Anton Johansson1-1/+1
2023-03-01target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`Anton Johansson2-16/+16
2023-02-28accel/tcg: Add 'size' param to probe_access_fullRichard Henderson1-2/+2
2023-02-27target/i386: Fix BZHI instructionRichard Henderson1-7/+7
2023-02-16target/i386: Fix 32-bit AD[CO]X insns in 64-bit modeRichard Henderson1-0/+2
2023-02-11target/i386: fix ADOX followed by ADCXPaolo Bonzini1-9/+11
2023-02-11target/i386: Fix C flag for BLSI, BLSMSK, BLSRRichard Henderson1-0/+3
2023-02-11target/i386: Fix BEXTR instructionRichard Henderson1-11/+11
2023-02-04target/i386: Inline cmpxchg16bRichard Henderson2-74/+39
2023-02-04target/i386: Inline cmpxchg8bRichard Henderson2-62/+49
2023-02-04target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16bRichard Henderson1-17/+31
2023-01-11target/i386: fix operand size of unary SSE operationsPaolo Bonzini1-5/+6