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AgeCommit message (Expand)AuthorFilesLines
2024-10-31target/i386: use + to put flags togetherPaolo Bonzini1-12/+12
2024-10-31target/i386: use higher-precision arithmetic to compute CFPaolo Bonzini1-0/+37
2024-10-31target/i386: use compiler builtin to compute PFPaolo Bonzini4-48/+17
2024-10-31target/i386: make flag variables unsignedPaolo Bonzini1-23/+23
2024-10-31target/i386: add a note about gen_jcc1Paolo Bonzini1-0/+4
2024-10-31target/i386: add a few more trivial CCPrepare casesPaolo Bonzini1-0/+3
2024-10-31target/i386: optimize TEST+Jxx sequencesPaolo Bonzini1-0/+22
2024-10-31target/i386: optimize computation of ZF from CC_OP_DYNAMICPaolo Bonzini2-3/+20
2024-10-31target/i386: Wrap cc_op_live with a validity checkRichard Henderson3-6/+21
2024-10-31target/i386: Introduce cc_op_sizeRichard Henderson2-12/+10
2024-10-31target/i386: remove CC_OP_CLRPaolo Bonzini3-24/+4
2024-10-31target/i386: use tcg_gen_ext_tl when applicablePaolo Bonzini1-8/+8
2024-10-30target/i386: fix CPUID check for LFENCE and SFENCEPaolo Bonzini1-2/+2
2024-10-22target/i386: Remove ra parameter from ptw_translateRichard Henderson1-9/+9
2024-10-22target/i386: Use probe_access_full_mmu in ptw_translateRichard Henderson1-6/+4
2024-10-22target/i386: Walk NPT in guest real modeAlexander Graf1-3/+14
2024-10-17target/i386: Use only 16 and 32-bit operands for IN/OUTRichard Henderson1-4/+4
2024-10-17target/i386/tcg: Use DPL-level accesses for interrupts and call gatesPaolo Bonzini1-6/+11
2024-10-17target/i386: assert that cc_op* and pc_save are preservedPaolo Bonzini1-9/+3
2024-10-17target/i386: list instructions still in translate.cPaolo Bonzini1-0/+31
2024-10-17target/i386: do not check PREFIX_LOCK in old-style decoderPaolo Bonzini1-18/+8
2024-10-17target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoderPaolo Bonzini4-129/+124
2024-10-17target/i386: decode address before going back to translate.cPaolo Bonzini4-118/+103
2024-10-17target/i386: convert bit test instructions to new decoderPaolo Bonzini4-158/+183
2024-08-21target/i386: Fix tss access size in switch_tss_raRichard Henderson1-2/+3
2024-08-21target/i386: Fix carry flag for BLSIRichard Henderson4-1/+42
2024-08-21target/i386: Split out gen_prepare_val_nzRichard Henderson1-8/+14
2024-08-16target/i386: allow access_ptr to force slow path on failed probeAlex Bennée1-14/+13
2024-08-13target/i386: Assert MMX and XMM registers in rangeRichard Henderson1-2/+7
2024-08-13target/i386: Use unit not type in decode_modrmRichard Henderson1-4/+4
2024-08-13target/i386: Do not apply REX to MMX operandsRichard Henderson1-1/+4
2024-08-05target/i386: Fix VSIB decodeRichard Henderson2-11/+12
2024-07-29target/i386: Remove dead assignment to ss in do_interrupt64()Peter Maydell1-3/+2
2024-07-16target/i386/tcg: save current task state before loading new onePaolo Bonzini1-40/+45
2024-07-16target/i386/tcg: use X86Access for TSS accessPaolo Bonzini1-52/+58
2024-07-16target/i386/tcg: check for correct busy state before switching to a new taskPaolo Bonzini1-0/+5
2024-07-16target/i386/tcg: Compute MMU index oncePaolo Bonzini1-13/+22
2024-07-16target/i386/tcg: Reorg push/pop within seg_helper.cRichard Henderson1-222/+259
2024-07-16target/i386/tcg: use PUSHL/PUSHW for error codePaolo Bonzini1-9/+7
2024-07-16target/i386/tcg: Allow IRET from user mode to user mode with SMAPPaolo Bonzini1-9/+9
2024-07-16target/i386/tcg: Remove SEG_ADDLRichard Henderson1-6/+2
2024-07-16target/i386/tcg: fix POP to memory in long modePaolo Bonzini2-1/+2
2024-06-28target/i386: remove unused enumPaolo Bonzini1-16/+0
2024-06-28target/i386: give CC_OP_POPCNT low bits corresponding to MO_TLPaolo Bonzini1-2/+1
2024-06-28target/i386: use cpu_cc_dst for CC_OP_POPCNTPaolo Bonzini3-5/+5
2024-06-17target/i386: convert CMPXCHG to new decoderPaolo Bonzini3-80/+53
2024-06-17target/i386: convert XADD to new decoderPaolo Bonzini3-36/+26
2024-06-17target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT to new decoderPaolo Bonzini4-76/+133
2024-06-17target/i386: convert SHLD/SHRD to new decoderPaolo Bonzini3-84/+50
2024-06-17target/i386: adapt gen_shift_count for SHLD/SHRDPaolo Bonzini1-10/+10