riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-05-10	target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu	Claudio Fontana	1	-0/+10
2021-05-10	target/i386: gdbstub: introduce aux functions to read/write CS64 regs	Claudio Fontana	1	-104/+51
2021-01-12	target/i386: Use X86Seg enum for segment registers	Philippe Mathieu-Daudé	1	-1/+1
2020-11-15	x86 tcg cpus: Fix Lesser GPL version number	Chetan Pant	1	-1/+1
2020-07-10	target/i386: fix IEEE SSE floating-point exception raising	Joseph Myers	1	-0/+1
2020-04-15	gdbstub: i386: Fix gdb_get_reg16() parameter to unbreak gdb	Peter Xu	1	-1/+1
2020-03-17	gdbstub: extend GByteArray to read register helpers	Alex Bennée	1	-1/+1
2020-03-17	target/i386: use gdb_get_reg helpers	Alex Bennée	1	-16/+11
2020-01-07	target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub	mkdolata@us.ibm.com	1	-2/+2
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-02-05	gdbstub: Fix i386/x86_64 machine description and add control registers	Doug Gale	1	-4/+189
2016-12-22	x86: Fix x86_64 'g' packet response to gdb from 32-bit mode.	Doug Evans	1	-13/+39
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+234