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path: root/target/hppa/translate.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller1-5/+43
2023-11-06target/hppa: Implement pa2.0 data prefetch instructionsRichard Henderson1-1/+9
2023-11-06target/hppa: Return zero for r0 from load_gprRichard Henderson1-3/+1
2023-11-06target/hppa: Precompute zero into DisasContextRichard Henderson1-16/+18
2023-11-06target/hppa: Implement PERMHRichard Henderson1-0/+29
2023-11-06target/hppa: Implement MIXH, MIXWRichard Henderson1-0/+55
2023-11-06target/hppa: Implement HSHLADD, HSHRADDRichard Henderson1-0/+32
2023-11-06target/hppa: Implement HSHL, HSHRRichard Henderson1-0/+35
2023-11-06target/hppa: Implement HAVGRichard Henderson1-0/+5
2023-11-06target/hppa: Implement HSUBRichard Henderson1-0/+15
2023-11-06target/hppa: Implement HADDRichard Henderson1-0/+37
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson1-4/+4
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson1-80/+82
2023-11-06target/hppa: Remove remaining TARGET_REGISTER_BITS redirectionsRichard Henderson1-33/+13
2023-11-06target/hppa: Remove most of the TARGET_REGISTER_BITS redirectionsRichard Henderson1-505/+407
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson1-148/+38
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson1-6/+36
2023-11-06target/hppa: Implement STDBYRichard Henderson1-0/+34
2023-11-06target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOMRichard Henderson1-0/+6
2023-11-06target/hppa: Implement SHRPDRichard Henderson1-30/+69
2023-11-06target/hppa: Implement EXTRDRichard Henderson1-11/+31
2023-11-06target/hppa: Implement DEPD, DEPDIRichard Henderson1-26/+54
2023-11-06target/hppa: Implement LDD, LDCD, LDDA, STD, STDARichard Henderson1-0/+4
2023-11-06target/hppa: Decode ADDB double-wordRichard Henderson1-0/+11
2023-11-06target/hppa: Decode CMPIB double-wordRichard Henderson1-1/+10
2023-11-06target/hppa: Decode d for cmpb instructionsRichard Henderson1-4/+8
2023-11-06target/hppa: Decode d for bb instructionsRichard Henderson1-4/+2
2023-11-06target/hppa: Decode d for sub instructionsRichard Henderson1-11/+11
2023-11-06target/hppa: Decode d for add instructionsRichard Henderson1-10/+11
2023-11-06target/hppa: Decode d for cmpclr instructionsRichard Henderson1-6/+5
2023-11-06target/hppa: Decode d for unit instructionsRichard Henderson1-13/+12
2023-11-06target/hppa: Decode d for logical instructionsRichard Henderson1-8/+7
2023-11-06target/hppa: Remove TARGET_HPPA64Richard Henderson1-2/+0
2023-11-06target/hppa: Pass d to do_unit_condRichard Henderson1-9/+11
2023-11-06target/hppa: Pass d to do_sed_condRichard Henderson1-11/+13
2023-11-06target/hppa: Pass d to do_log_condRichard Henderson1-10/+38
2023-11-06target/hppa: Pass d to do_sub_condRichard Henderson1-26/+47
2023-11-06target/hppa: Pass d to do_condRichard Henderson1-28/+54
2023-11-06target/hppa: sar register allows only 5 bits on 32-bit CPUHelge Deller1-2/+2
2023-11-06target/hppa: Mask inputs in copy_iaoq_entryRichard Henderson1-2/+14
2023-11-06target/hppa: Use copy_iaoq_entry for link in do_ibranchRichard Henderson1-1/+1
2023-11-06target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]Richard Henderson1-13/+22
2023-11-06target/hppa: Pass DisasContext to copy_iaoq_entryRichard Henderson1-19/+20
2023-11-06target/hppa: Fix hppa64 addressingRichard Henderson1-9/+13
2023-11-06target/hppa: Introduce TYPE_HPPA64_CPURichard Henderson1-0/+2
2023-11-06target/hppa: Fix extrw and depw with sar for hppa64Richard Henderson1-2/+5
2023-11-06target/hppa: Fix bb_sar for hppa64Richard Henderson1-3/+13
2023-11-06target/hppa: Fix do_add, do_sub for hppa64Richard Henderson1-18/+32
2023-11-06target/hppa: Fix trans_ds for hppa64Richard Henderson1-11/+37
2023-11-06target/hppa: Truncate rotate count in trans_shrpw_sarRichard Henderson1-1/+4