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path: root/target/hexagon/translate.c
AgeCommit message (Expand)AuthorFilesLines
2023-04-21Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_storesTaylor Simpson1-5/+5
2023-04-21Hexagon (translate.c): avoid redundant PC updates on COFMatheus Tavares Bernardino1-8/+13
2023-03-06Hexagon (target/hexagon) Improve code gen for predicated HVX instructionsTaylor Simpson1-52/+6
2023-03-06Hexagon (target/hexagon) Reduce manipulation of slot_cancelledTaylor Simpson1-6/+36
2023-03-06Hexagon (target/hexagon) Analyze packet for HVXTaylor Simpson1-0/+30
2023-03-06Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not neededTaylor Simpson1-1/+5
2023-03-06Hexagon (target/hexagon) Analyze packet before generating TCGTaylor Simpson1-63/+99
2023-03-05target/hexagon: Drop tcg_temp_free from C codeRichard Henderson1-7/+0
2023-03-01target/hexagon: Don't use tcg_temp_local_new_*Richard Henderson1-1/+1
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2022-12-16Hexagon (target/hexagon) Use direct block chaining for tight loopsTaylor Simpson1-0/+33
2022-12-16Hexagon (target/hexagon) Use direct block chaining for direct jump/branchTaylor Simpson1-1/+33
2022-12-16Hexagon (target/hexagon) Remove next_PC from runtime stateTaylor Simpson1-6/+23
2022-12-16Hexagon (target/hexagon) Remove PC from the runtime stateTaylor Simpson1-8/+1
2022-12-16Hexagon (target/hexagon) Only use branch_taken when packet has multi cofTaylor Simpson1-1/+3
2022-12-16Hexagon (target/hexagon) Add pkt and insn to DisasContextTaylor Simpson1-57/+63
2022-09-30Hexagon (target/hexagon) move store size tracking to translationTaylor Simpson1-0/+25
2022-09-30Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]Taylor Simpson1-4/+6
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+4
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
2022-04-20target/hexagon: Remove qemu_set_log in hexagon_translate_initRichard Henderson1-6/+0
2021-11-03Hexagon HVX (target/hexagon) TCG generationTaylor Simpson1-4/+235
2021-10-28Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson1-1/+8
2021-10-28Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson1-2/+1
2021-10-15target/hexagon: Drop checks for singlestep_enabledRichard Henderson1-10/+2
2021-10-06target/hexagon: Use tcg_constant_*Philippe Mathieu-Daudé1-18/+8
2021-10-06Hexagon (target/hexagon) probe the stores in a packet at start of commitTaylor Simpson1-3/+35
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-1/+2
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-17/+0
2021-06-29Hexagon (target/hexagon) remove unused TCG variablesTaylor Simpson1-9/+2
2021-05-01Hexagon (target/hexagon) compile all debug codeTaylor Simpson1-39/+35
2021-05-01Hexagon (target/hexagon) change variables from int to bool when appropriateTaylor Simpson1-3/+3
2021-05-01Hexagon (target/hexagon) decide if pred has been written at TCG gen timeTaylor Simpson1-2/+7
2021-05-01Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURNTaylor Simpson1-29/+33
2021-05-01Hexagon (target/hexagon) use env_archcpu and env_cpuTaylor Simpson1-1/+1
2021-05-01Hexagon (target/hexagon) remove unnecessary inline directivesTaylor Simpson1-1/+1
2021-05-01target/hexagon: translation changesTaylor Simpson1-17/+9
2021-02-18Hexagon (target/hexagon) translationTaylor Simpson1-0/+748