riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-10-15	target/avr: Drop checks for singlestep_enabled	Richard Henderson	1	-15/+4
2021-09-16	target/avr: Fix compiler errors (-Werror=enum-conversion)	Stefan Weil	1	-5/+3
2021-07-21	accel/tcg: Remove TranslatorOps.breakpoint_check	Richard Henderson	1	-18/+0
2021-07-21	target/avr: Implement gdb_adjust_breakpoint	Richard Henderson	1	-14/+0
2021-07-09	target/avr: Use translator_use_goto_tb	Richard Henderson	1	-3/+6
2021-06-29	target/avr: Convert to TranslatorOps	Richard Henderson	1	-104/+126
2021-06-29	target/avr: Change ctx to DisasContext* in gen_intermediate_code	Richard Henderson	1	-41/+43
2021-06-29	target/avr: Add DisasContextBase to DisasContext	Richard Henderson	1	-29/+29
2020-08-21	meson: target	Paolo Bonzini	1	-1/+1
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	1	-1/+1
2020-07-11	target/avr: Add support for disassembling via option '-d in_asm'	Michael Rolnik	1	-0/+12
2020-07-11	target/avr: Initialize TCG register variables	Michael Rolnik	1	-0/+29
2020-07-11	target/avr: Add instruction translation - CPU main translation function	Michael Rolnik	1	-0/+213
2020-07-11	target/avr: Add instruction translation - MCU Control Instructions	Michael Rolnik	1	-0/+65
2020-07-11	target/avr: Add instruction translation - Bit and Bit-test Instructions	Michael Rolnik	1	-0/+247
2020-07-11	target/avr: Add instruction translation - Data Transfer Instructions	Michael Rolnik	1	-0/+990
2020-07-11	target/avr: Add instruction translation - Branch Instructions	Michael Rolnik	1	-0/+543
2020-07-11	target/avr: Add instruction translation - Arithmetic and Logic Instructions	Michael Rolnik	1	-0/+820
2020-07-11	target/avr: Add instruction translation - Register definitions	Michael Rolnik	1	-0/+142