riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-10-24	target/arm: Use gvec for NEON_3R_VMUL	Richard Henderson	1	-16/+15
2018-10-24	target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG	Richard Henderson	1	-8/+8
2018-10-24	target/arm: Use gvec for NEON_3R_VADD_VSUB insns	Richard Henderson	1	-19/+10
2018-10-24	target/arm: Use gvec for NEON_3R_LOGIC insns	Richard Henderson	3	-105/+124
2018-10-24	target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)	Richard Henderson	1	-25/+36
2018-10-24	target/arm: Use gvec for NEON VDUP	Richard Henderson	1	-27/+36
2018-10-24	target/arm: Mark some arrays const	Richard Henderson	1	-2/+2
2018-10-24	target/arm: Promote consecutive memory ops for aa64	Richard Henderson	1	-26/+40
2018-10-24	target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R	Richard Henderson	1	-25/+3
2018-10-24	target/arm: Don't call tcg_clear_temp_count	Richard Henderson	2	-2/+0
2018-10-24	target/arm: Hoist address increment for vector memory ops	Richard Henderson	1	-4/+8
2018-10-24	target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode	Peter Maydell	3	-5/+26
2018-10-24	target/arm: Get IL bit correct for v7 syndrome values	Peter Maydell	2	-5/+15
2018-10-24	target/arm: New utility function to extract EC from syndrome	Peter Maydell	4	-4/+9
2018-10-24	target/arm: Implement HCR.PTW	Peter Maydell	1	-1/+20
2018-10-24	target/arm: Implement HCR.VI and VF	Peter Maydell	1	-4/+43
2018-10-24	target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set	Peter Maydell	1	-4/+18
2018-10-24	target/arm: Implement HCR.DC	Peter Maydell	1	-2/+21
2018-10-24	target/arm: Implement HCR.FB	Peter Maydell	1	-72/+113
2018-10-24	target/arm: Make switch_mode() file-local	Peter Maydell	2	-3/+4
2018-10-24	target/arm: Improve debug logging of AArch32 exception return	Peter Maydell	3	-6/+29
2018-10-24	target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test	Richard Henderson	5	-32/+49
2018-10-24	target/arm: Convert sve from feature bit to aa64pfr0 test	Richard Henderson	5	-9/+28
2018-10-24	target/arm: Convert jazelle from feature bit to isar1 test	Richard Henderson	3	-5/+20
2018-10-24	target/arm: Convert division from feature bits to isar0 tests	Richard Henderson	3	-13/+13
2018-10-24	target/arm: Convert v8 extensions from feature bits to isar tests	Richard Henderson	6	-114/+245
2018-10-24	target/arm: V8M should not imply V7VE	Richard Henderson	1	-1/+5
2018-10-24	target/arm: Move some system registers into a substructure	Richard Henderson	4	-152/+156
2018-10-24	target/arm: Add support for VCPU event states	Dongjiu Geng	6	-0/+139
2018-10-18	target/arm: Check HAVE_CMPXCHG128 at translate time	Richard Henderson	2	-28/+26
2018-10-18	target/arm: Convert to HAVE_CMPXCHG128	Richard Henderson	1	-127/+134
2018-10-16	target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write	Peter Maydell	1	-2/+2
2018-10-16	target/arm: Mask PMOVSR writes based on supported counters	Aaron Lindsay	1	-0/+1
2018-10-16	target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO	Aaron Lindsay	1	-2/+4
2018-10-16	target/arm: Add the Cortex-A72	Edgar E. Iglesias	1	-3/+63
2018-10-16	target-arm: powerctl: Enable HVC when starting CPUs to EL2	Edgar E. Iglesias	1	-0/+10
2018-10-16	target/arm: Fix cortex-a7 id_isar0	Richard Henderson	1	-1/+4
2018-10-16	target/arm: Align cortex-r5 id_isar0	Richard Henderson	1	-1/+1
2018-10-16	target/arm: Define fields of ISAR registers	Richard Henderson	1	-0/+88
2018-10-16	target/arm: Fix aarch64_sve_change_el wrt EL0	Richard Henderson	3	-7/+22
2018-10-08	target/arm: Add v8M stack checks for MSR to SP_NS	Peter Maydell	1	-1/+13
2018-10-08	target/arm: Add v8M stack checks for VLDM/VSTM	Peter Maydell	1	-0/+12
2018-10-08	target/arm: Add v8M stack checks for Thumb push/pop	Peter Maydell	1	-1/+15
2018-10-08	target/arm: Add v8M stack checks for T32 load/store single	Peter Maydell	1	-1/+22
2018-10-08	target/arm: Add v8M stack checks for Thumb2 LDM/STM	Peter Maydell	1	-1/+18
2018-10-08	target/arm: Add v8M stack checks for LDRD/STRD (imm)	Peter Maydell	1	-2/+25
2018-10-08	target/arm: Add v8M stack limit checks on NS function calls	Peter Maydell	3	-2/+15
2018-10-08	target/arm: Add v8M stack checks on exception entry	Peter Maydell	1	-8/+46
2018-10-08	target/arm: Add some comments in Thumb decode	Peter Maydell	1	-3/+17
2018-10-08	target/arm: Add v8M stack checks on ADD/SUB/MOV of SP	Peter Maydell	4	-9/+106