| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-02-21 | target/arm: Convert PMULL.8 to gvec | Richard Henderson | 1 | -13/+13 |
| 2020-02-21 | target/arm: Convert PMULL.64 to gvec | Richard Henderson | 1 | -14/+2 |
| 2020-02-21 | target/arm: Convert PMUL.8 to gvec | Richard Henderson | 1 | -7/+4 |
| 2020-02-21 | target/arm: Vectorize USHL and SSHL | Richard Henderson | 1 | -15/+284 |
| 2020-02-21 | target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers | Peter Maydell | 1 | -3/+3 |
| 2020-02-13 | target/arm: Split out aarch32_cpsr_valid_mask | Richard Henderson | 1 | -23/+17 |
| 2020-02-13 | target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled | Richard Henderson | 1 | -0/+2 |
| 2020-02-07 | target/arm: Reorganize ARMMMUIdx | Richard Henderson | 1 | -1/+0 |
| 2020-02-07 | target/arm: Recover 4 bits from TBFLAGs | Richard Henderson | 1 | -26/+33 |
| 2020-02-07 | target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 | Richard Henderson | 1 | -1/+1 |
| 2020-02-07 | target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 | Richard Henderson | 1 | -1/+1 |
| 2020-02-07 | target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] | Richard Henderson | 1 | -3/+3 |
| 2020-02-07 | target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 | Richard Henderson | 1 | -1/+1 |
| 2020-02-07 | target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* | Richard Henderson | 1 | -3/+3 |
| 2020-01-17 | target/arm: Set ISSIs16Bit in make_issinfo | Richard Henderson | 1 | -0/+3 |
| 2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé | 1 | -2/+2 |
| 2020-01-09 | target/arm: only update pc after semihosting completes | Alex Bennée | 1 | -3/+3 |
| 2019-12-16 | target/arm: ensure we use current exception state after SCR update | Alex Bennée | 1 | -1/+5 |
| 2019-12-16 | target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 | Marc Zyngier | 1 | -1/+2 |
| 2019-11-19 | target/arm: Relax r13 restriction for ldrex/strex for v8.0 | Richard Henderson | 1 | -4/+8 |
| 2019-11-19 | target/arm: Do not reject rt == rt2 for strexd | Richard Henderson | 1 | -1/+1 |
| 2019-10-24 | target/arm: Rebuild hflags for M-profile | Richard Henderson | 1 | -1/+4 |
| 2019-10-24 | target/arm: Rebuild hflags at MSR writes | Richard Henderson | 1 | -5/+23 |
| 2019-10-22 | target/arm: Fix sign-extension for SMLAL* | Richard Henderson | 1 | -1/+3 |
| 2019-09-27 | target/arm: handle A-profile semihosting at translate time | Alex Bennée | 1 | -4/+15 |
| 2019-09-27 | target/arm: handle M-profile semihosting at translate time | Alex Bennée | 1 | -1/+10 |
| 2019-09-05 | target/arm: Inline gen_bx_im into callers | Richard Henderson | 1 | -19/+7 |
| 2019-09-05 | target/arm: Clean up disas_thumb_insn | Richard Henderson | 1 | -25/+2 |
| 2019-09-05 | target/arm: Convert T16, long branches | Richard Henderson | 1 | -49/+36 |
| 2019-09-05 | target/arm: Convert T16, Unconditional branch | Richard Henderson | 1 | -7/+2 |
| 2019-09-05 | target/arm: Convert T16, load (literal) | Richard Henderson | 1 | -40/+2 |
| 2019-09-05 | target/arm: Convert T16, shift immediate | Richard Henderson | 1 | -24/+2 |
| 2019-09-05 | target/arm: Convert T16, Miscellaneous 16-bit instructions | Richard Henderson | 1 | -77/+34 |
| 2019-09-05 | target/arm: Convert T16, Conditional branches, Supervisor call | Richard Henderson | 1 | -23/+3 |
| 2019-09-05 | target/arm: Convert T16, push and pop | Richard Henderson | 1 | -71/+12 |
| 2019-09-05 | target/arm: Split gen_nop_hint | Richard Henderson | 1 | -43/+24 |
| 2019-09-05 | target/arm: Convert T16, nop hints | Richard Henderson | 1 | -2/+1 |
| 2019-09-05 | target/arm: Convert T16, Reverse bytes | Richard Henderson | 1 | -15/+3 |
| 2019-09-05 | target/arm: Convert T16, Change processor state | Richard Henderson | 1 | -46/+38 |
| 2019-09-05 | target/arm: Convert T16, extract | Richard Henderson | 1 | -13/+1 |
| 2019-09-05 | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson | 1 | -13/+2 |
| 2019-09-05 | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson | 1 | -47/+2 |
| 2019-09-05 | target/arm: Convert T16 branch and exchange | Richard Henderson | 1 | -41/+29 |
| 2019-09-05 | target/arm: Convert T16 one low register and immediate | Richard Henderson | 1 | -42/+2 |
| 2019-09-05 | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 1 | -24/+2 |
| 2019-09-05 | target/arm: Convert T16 load/store multiple | Richard Henderson | 1 | -39/+9 |
| 2019-09-05 | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 1 | -11/+1 |
| 2019-09-05 | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 1 | -89/+5 |
| 2019-09-05 | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 1 | -49/+2 |
| 2019-09-05 | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 1 | -145/+7 |
