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author | Alex Bennée <alex.bennee@linaro.org> | 2019-12-12 11:47:34 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2019-12-16 10:52:58 +0000 |
commit | f80741d107673f162e3b097fc76a1590036cc9d1 (patch) | |
tree | 3df13acac91a2fd4aa12312fc3216f55a21102f0 /target/arm/translate.c | |
parent | b8b69f4c45894ea05a9c334e76178679ec084565 (diff) | |
download | qemu-f80741d107673f162e3b097fc76a1590036cc9d1.zip qemu-f80741d107673f162e3b097fc76a1590036cc9d1.tar.gz qemu-f80741d107673f162e3b097fc76a1590036cc9d1.tar.bz2 |
target/arm: ensure we use current exception state after SCR update
A write to the SCR can change the effective EL by droppping the system
from secure to non-secure mode. However if we use a cached current_el
from before the change we'll rebuild the flags incorrectly. To fix
this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL
should be used when recomputing the flags.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191212114734.6962-1-alex.bennee@linaro.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org>
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
-rw-r--r-- | target/arm/translate.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index f162be8..2b6c1f9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7083,7 +7083,11 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) if (arm_dc_feature(s, ARM_FEATURE_M)) { gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); } else { - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + if (ri->type & ARM_CP_NEWEL) { + gen_helper_rebuild_hflags_a32_newel(cpu_env); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } } tcg_temp_free_i32(tcg_el); /* |