riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-03-12	target/arm: Update sve reduction vs simd_desc	Richard Henderson	1	-1/+1
2021-03-12	target/arm: Update WHILE for PREDDESC	Richard Henderson	1	-3/+4
2021-03-12	target/arm: Update CNTP for PREDDESC	Richard Henderson	1	-3/+3
2021-03-12	target/arm: Update BRKA, BRKB, BRKN for PREDDESC	Richard Henderson	1	-2/+2
2021-03-12	target/arm: Update find_last_active for PREDDESC	Richard Henderson	1	-4/+3
2021-01-19	target/arm: Update REV, PUNPK for pred_desc	Richard Henderson	1	-9/+4
2021-01-19	target/arm: Update ZIP, UZP, TRN for pred_desc	Richard Henderson	1	-8/+4
2021-01-19	target/arm: Update PFIRST, PNEXT for pred_desc	Richard Henderson	1	-3/+3
2020-11-15	arm tcg cpus: Fix Lesser GPL version number	Chetan Pant	1	-1/+1
2020-10-01	target/arm: Fix SVE splice	Richard Henderson	1	-1/+1
2020-10-01	target/arm: Fix sve ldr/str	Richard Henderson	1	-2/+2
2020-09-01	target/arm: Remove local definitions of float constants	Peter Maydell	1	-4/+0
2020-08-28	target/arm: Split out gen_gvec_ool_zz	Richard Henderson	1	-8/+12
2020-08-28	target/arm: Split out gen_gvec_ool_zzz	Richard Henderson	1	-35/+18
2020-08-28	target/arm: Split out gen_gvec_ool_zzp	Richard Henderson	1	-15/+14
2020-08-28	target/arm: Merge helper_sve_clr_* and helper_sve_movz_*	Richard Henderson	1	-32/+17
2020-08-28	target/arm: Split out gen_gvec_ool_zzzp	Richard Henderson	1	-19/+16
2020-08-28	target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp	Richard Henderson	1	-23/+8
2020-08-28	target/arm: Clean up 4-operand predicate expansion	Richard Henderson	1	-68/+43
2020-08-28	target/arm: Merge do_vector2_p into do_mov_p	Richard Henderson	1	-13/+6
2020-08-28	target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn	Richard Henderson	1	-19/+24
2020-08-28	target/arm: Split out gen_gvec_fn_zz	Richard Henderson	1	-9/+10
2020-08-24	target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()	Peter Maydell	1	-17/+17
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	1	-1/+1
2020-07-13	target/arm: Fix mtedesc for do_mem_zpz	Richard Henderson	1	-1/+1
2020-07-03	target/arm: Fix temp double-free in sve ldr/str	Richard Henderson	1	-6/+2
2020-06-26	target/arm: Add mte helpers for sve scatter/gather memory ops	Richard Henderson	1	-222/+440
2020-06-26	target/arm: Handle TBI for sve scalar + int memory ops	Richard Henderson	1	-2/+4
2020-06-26	target/arm: Add mte helpers for sve scalar + int ff/nf loads	Richard Henderson	1	-88/+172
2020-06-26	target/arm: Add mte helpers for sve scalar + int stores	Richard Henderson	1	-55/+107
2020-06-26	target/arm: Add mte helpers for sve scalar + int loads	Richard Henderson	1	-59/+141
2020-06-26	target/arm: Tidy trans_LD1R_zpri	Richard Henderson	1	-5/+7
2020-06-26	target/arm: Use mte_check1 for sve LD1R	Richard Henderson	1	-2/+4
2020-06-26	target/arm: Use mte_checkN for sve unpredicated stores	Richard Henderson	1	-28/+33
2020-06-26	target/arm: Use mte_checkN for sve unpredicated loads	Richard Henderson	1	-28/+33
2020-05-11	target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)	Richard Henderson	1	-1/+5
2020-05-11	target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA	Richard Henderson	1	-46/+24
2020-05-11	target/arm: Remove sve_memopidx	Richard Henderson	1	-14/+3
2020-05-06	target/arm: Use tcg_gen_gvec_dup_imm	Richard Henderson	1	-7/+5
2020-01-15	tcg: Search includes from the project root source directory	Philippe Mathieu-Daudé	1	-3/+3
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen	1	-1/+1
2019-05-13	tcg: Specify optional vector requirements with a list	Richard Henderson	1	-4/+5
2019-05-06	decodetree: Add DisasContext argument to !function expanders	Richard Henderson	1	-12/+12
2019-03-15	target/arm: Check access permission to ADDVL/ADDPL/RDVL	Amir Charif	1	-8/+14
2019-02-15	target/arm: Rely on optimization within tcg_gen_gvec_or	Richard Henderson	1	-5/+1
2018-10-31	decodetree: Remove "insn" argument from trans_* expanders	Richard Henderson	1	-263/+244
2018-10-08	target/arm: Pass TCGMemOpIdx to sve memory helpers	Richard Henderson	1	-23/+44
2018-10-08	target/arm: Rewrite vector gather first-fault loads	Richard Henderson	1	-42/+42
2018-10-08	target/arm: Rewrite vector gather stores	Richard Henderson	1	-25/+49
2018-10-08	target/arm: Rewrite vector gather loads	Richard Henderson	1	-81/+167