| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-07-11 | target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree | Richard Henderson | 2 | -499/+138 |
| 2024-07-11 | target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree | Richard Henderson | 2 | -72/+87 |
| 2024-07-11 | target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree | Richard Henderson | 2 | -50/+156 |
| 2024-07-11 | target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() | Peter Maydell | 1 | -0/+1 |
| 2024-07-11 | target/arm: Rename FPCR_ QC, NZCV macros to FPSR_ | Peter Maydell | 3 | -13/+13 |
| 2024-07-11 | target/arm: Store FPSR and FPCR in separate CPU state fields | Peter Maydell | 4 | -12/+11 |
| 2024-07-11 | target/arm: Implement store_cpu_field_low32() macro | Peter Maydell | 1 | -0/+7 |
| 2024-07-05 | target/arm: Make some MTE helpers widely available | Gustavo Romero | 2 | -38/+73 |
| 2024-07-05 | target/arm: Fix exception case in allocation_tag_mem_probe | Gustavo Romero | 1 | -0/+3 |
| 2024-07-01 | target/arm: Enable FEAT_Debugv8p8 for -cpu max | Gustavo Romero | 2 | -4/+4 |
| 2024-07-01 | target/arm: Move initialization of debug ID registers | Gustavo Romero | 1 | -3/+28 |
| 2024-07-01 | target/arm: Fix indentation | Gustavo Romero | 1 | -1/+1 |
| 2024-07-01 | target/arm: Delete dead code from disas_simd_indexed | Richard Henderson | 1 | -93/+0 |
| 2024-07-01 | target/arm: Convert FCMLA to decodetree | Richard Henderson | 2 | -170/+74 |
| 2024-07-01 | target/arm: Convert FCADD to decodetree | Richard Henderson | 2 | -23/+13 |
| 2024-07-01 | target/arm: Add data argument to do_fp3_vector | Richard Henderson | 1 | -26/+26 |
| 2024-07-01 | target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree | Richard Henderson | 2 | -28/+12 |
| 2024-07-01 | target/arm: Convert BFMLALB, BFMLALT to decodetree | Richard Henderson | 2 | -48/+31 |
| 2024-07-01 | target/arm: Convert BFDOT to decodetree | Richard Henderson | 2 | -15/+7 |
| 2024-07-01 | target/arm: Convert SUDOT, USDOT to decodetree | Richard Henderson | 2 | -27/+11 |
| 2024-07-01 | target/arm: Convert SDOT, UDOT to decodetree | Richard Henderson | 2 | -26/+35 |
| 2024-07-01 | target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree | Richard Henderson | 3 | -124/+170 |
| 2024-07-01 | target/arm: Fix SQDMULH (by element) with Q=0 | Richard Henderson | 1 | -8/+16 |
| 2024-07-01 | target/arm: Fix VCMLA Dd, Dn, Dm[idx] | Richard Henderson | 1 | -2/+2 |
| 2024-05-30 | target/arm: Implement FEAT WFxT and enable for '-cpu max' | Peter Maydell | 4 | -0/+100 |
| 2024-05-30 | target/arm: Convert FCSEL to decodetree | Richard Henderson | 2 | -63/+49 |
| 2024-05-30 | target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree | Richard Henderson | 2 | -148/+93 |
| 2024-05-30 | target/arm: Convert SQDMULH, SQRDMULH to decodetree | Richard Henderson | 3 | -196/+162 |
| 2024-05-30 | target/arm: Tidy SQDMULH, SQRDMULH (vector) | Richard Henderson | 4 | -39/+31 |
| 2024-05-30 | target/arm: Convert MLA, MLS to decodetree | Richard Henderson | 2 | -54/+31 |
| 2024-05-30 | target/arm: Convert MUL, PMUL to decodetree | Richard Henderson | 2 | -31/+25 |
| 2024-05-30 | target/arm: Convert SABA, SABD, UABA, UABD to decodetree | Richard Henderson | 2 | -16/+10 |
| 2024-05-30 | target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree | Richard Henderson | 2 | -16/+10 |
| 2024-05-30 | target/arm: Convert SRHADD, URHADD to decodetree | Richard Henderson | 2 | -8/+5 |
| 2024-05-30 | target/arm: Convert SRHADD, URHADD to gvec | Richard Henderson | 5 | -91/+158 |
| 2024-05-30 | target/arm: Convert SHSUB, UHSUB to decodetree | Richard Henderson | 2 | -8/+5 |
| 2024-05-30 | target/arm: Convert SHSUB, UHSUB to gvec | Richard Henderson | 5 | -39/+157 |
| 2024-05-30 | target/arm: Convert SHADD, UHADD to decodetree | Richard Henderson | 2 | -8/+5 |
| 2024-05-30 | target/arm: Convert SHADD, UHADD to gvec | Richard Henderson | 5 | -39/+158 |
| 2024-05-30 | target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec | Richard Henderson | 1 | -3/+1 |
| 2024-05-30 | target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64} | Richard Henderson | 1 | -4/+2 |
| 2024-05-30 | target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree | Richard Henderson | 2 | -84/+60 |
| 2024-05-30 | target/arm: Convert ADD, SUB (vector) to decodetree | Richard Henderson | 2 | -15/+13 |
| 2024-05-30 | target/arm: Convert SQRSHL, UQRSHL to decodetree | Richard Henderson | 2 | -26/+26 |
| 2024-05-30 | target/arm: Convert SQRSHL and UQRSHL (register) to gvec | Richard Henderson | 6 | -72/+63 |
| 2024-05-30 | target/arm: Convert SQSHL, UQSHL to decodetree | Richard Henderson | 2 | -25/+53 |
| 2024-05-30 | target/arm: Convert SQSHL and UQSHL (register) to gvec | Richard Henderson | 6 | -22/+75 |
| 2024-05-30 | target/arm: Convert SRSHL, URSHL to decodetree | Richard Henderson | 2 | -15/+11 |
| 2024-05-30 | target/arm: Convert SRSHL and URSHL (register) to gvec | Richard Henderson | 6 | -23/+74 |
| 2024-05-30 | target/arm: Convert SSHL, USHL to decodetree | Richard Henderson | 2 | -15/+32 |
