| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-07-09 | target/arm: Use aesdec_IMC | Richard Henderson | 1 | -19/+14 |
| 2023-07-09 | target/arm: Use aesenc_MC | Richard Henderson | 1 | -1/+14 |
| 2023-07-09 | target/arm: Use aesdec_ISB_ISR_AK | Richard Henderson | 1 | -21/+16 |
| 2023-07-09 | target/arm: Use aesenc_SB_SR_AK | Richard Henderson | 1 | -1/+23 |
| 2023-07-08 | target/arm: Demultiplex AESE and AESMC | Richard Henderson | 5 | -27/+39 |
| 2023-07-08 | target/arm: Move aesmc and aesimc tables to crypto/aes.c | Richard Henderson | 1 | -138/+5 |
| 2023-07-06 | target/arm: Define neoverse-v1 | Peter Maydell | 1 | -0/+128 |
| 2023-07-06 | target/arm: Fix SME full tile indexing | Richard Henderson | 1 | -6/+18 |
| 2023-07-03 | plugins: force slow path when plugins instrument memory ops | Alex Bennée | 1 | -4/+0 |
| 2023-06-23 | target/arm: Fix sve predicate store, 8 <= VQ <= 15 | Richard Henderson | 1 | -1/+1 |
| 2023-06-23 | target/arm: Add cpu properties for enabling FEAT_RME | Richard Henderson | 1 | -0/+53 |
| 2023-06-23 | target/arm: Implement GPC exceptions | Richard Henderson | 1 | -3/+93 |
| 2023-06-20 | meson: Replace softmmu_ss -> system_ss | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2023-06-19 | target/arm: Convert load/store tags insns to decodetree | Peter Maydell | 2 | -177/+190 |
| 2023-06-19 | target/arm: Convert load/store single structure to decodetree | Peter Maydell | 2 | -108/+127 |
| 2023-06-19 | target/arm: Convert load/store (multiple structures) to decodetree | Peter Maydell | 2 | -108/+128 |
| 2023-06-19 | target/arm: Convert LDAPR/STLR (imm) to decodetree | Peter Maydell | 2 | -84/+54 |
| 2023-06-19 | target/arm: Convert load (pointer auth) insns to decodetree | Peter Maydell | 2 | -67/+23 |
| 2023-06-19 | target/arm: Convert atomic memory ops to decodetree | Peter Maydell | 2 | -98/+70 |
| 2023-06-19 | target/arm: Convert LDR/STR reg+reg to decodetree | Peter Maydell | 2 | -87/+98 |
| 2023-06-19 | target/arm: Convert LDR/STR with 12-bit immediate to decodetree | Peter Maydell | 2 | -88/+41 |
| 2023-06-19 | target/arm: Convert ld/st reg+imm9 insns to decodetree | Peter Maydell | 2 | -118/+149 |
| 2023-06-19 | target/arm: Convert load/store-pair to decodetree | Peter Maydell | 2 | -196/+249 |
| 2023-06-19 | target/arm: Convert load reg (literal) group to decodetree | Peter Maydell | 2 | -54/+35 |
| 2023-06-19 | target/arm: Convert LDXP, STXP, CASP, CAS to decodetree | Peter Maydell | 2 | -76/+50 |
| 2023-06-19 | target/arm: Convert load/store exclusive and ordered to decodetree | Peter Maydell | 2 | -62/+103 |
| 2023-06-19 | target/arm: Convert exception generation instructions to decodetree | Peter Maydell | 2 | -106/+76 |
| 2023-06-19 | target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree | Peter Maydell | 2 | -28/+14 |
| 2023-06-19 | target/arm: Convert MSR (immediate) to decodetree | Peter Maydell | 2 | -115/+123 |
| 2023-06-19 | target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree | Peter Maydell | 2 | -27/+32 |
| 2023-06-19 | target/arm: Convert barrier insns to decodetree | Peter Maydell | 2 | -53/+46 |
| 2023-06-19 | target/arm: Convert hint instruction space to decodetree | Peter Maydell | 2 | -123/+185 |
| 2023-06-19 | target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores | Peter Maydell | 1 | -4/+6 |
| 2023-06-19 | target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode | Peter Maydell | 1 | -1/+1 |
| 2023-06-19 | target/arm: Return correct result for LDG when ATA=0 | Peter Maydell | 1 | -1/+5 |
| 2023-06-19 | target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics | Peter Maydell | 1 | -2/+16 |
| 2023-06-06 | target/arm: Enable FEAT_LSE2 for -cpu max | Richard Henderson | 1 | -0/+1 |
| 2023-06-06 | target/arm: Move mte check for store-exclusive | Richard Henderson | 1 | -6/+36 |
| 2023-06-06 | target/arm: Relax ordered/atomic alignment checks for LSE2 | Richard Henderson | 3 | -26/+104 |
| 2023-06-06 | target/arm: Add SCTLR.nAA to TBFLAG_A64 | Richard Henderson | 3 | -0/+9 |
| 2023-06-06 | target/arm: Check alignment in helper_mte_check | Richard Henderson | 2 | -0/+20 |
| 2023-06-06 | target/arm: Pass single_memop to gen_mte_checkN | Richard Henderson | 3 | -15/+22 |
| 2023-06-06 | target/arm: Pass memop to gen_mte_check1* | Richard Henderson | 3 | -42/+49 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_fp_{ld, st} | Richard Henderson | 1 | -20/+23 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_gpr_{ld, st} | Richard Henderson | 1 | -26/+35 |
| 2023-06-06 | target/arm: Load/store integer pair with one tcg operation | Richard Henderson | 1 | -15/+55 |
| 2023-06-06 | target/arm: Sink gen_mte_check1 into load/store_exclusive | Richard Henderson | 1 | -23/+21 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r | Richard Henderson | 1 | -25/+70 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G | Richard Henderson | 1 | -7/+10 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} | Richard Henderson | 2 | -24/+35 |
