riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-27	target/arm: Fix A64 scalar SQSHRN and SQRSHRN	Peter Maydell	1	-1/+1
2023-11-13	target/arm: HVC at EL3 should go to EL3, not EL2	Peter Maydell	1	-1/+3
2023-10-27	target/arm: Fix syndrome for FGT traps on ERET	Peter Maydell	1	-2/+2
2023-10-22	target/arm: Use tcg_gen_ext_i64	Richard Henderson	1	-35/+2
2023-10-04	accel/tcg: Replace CPUState.env_ptr with cpu_env()	Richard Henderson	1	-2/+2
2023-10-03	tcg: Rename cpu_env to tcg_env	Richard Henderson	1	-189/+189
2023-10-03	target/arm: Replace TARGET_PAGE_ENTRY_EXTRA	Anton Johansson	1	-1/+1
2023-09-21	target/arm: Implement the CPY* instructions	Peter Maydell	1	-0/+60
2023-09-21	target/arm: Implement the SETG* instructions	Peter Maydell	1	-6/+14
2023-09-21	target/arm: Define new TB flag for ATA0	Peter Maydell	1	-11/+12
2023-09-21	target/arm: Implement the SET* instructions	Peter Maydell	1	-0/+49
2023-09-21	target/arm: Pass unpriv bool to get_a64_user_mem_index()	Peter Maydell	1	-6/+14
2023-09-21	target/arm: Implement FEAT_HBC	Peter Maydell	1	-0/+4
2023-09-08	target/arm: Implement FEAT_TIDCP1	Richard Henderson	1	-0/+5
2023-09-08	target/arm: Implement HCR_EL2.TIDCP	Richard Henderson	1	-2/+14
2023-09-08	target/arm: Do not use gen_mte_checkN in trans_STGP	Richard Henderson	1	-26/+15
2023-09-08	target/arm: Inform helpers whether a PAC instruction is 'combined'	Aaron Lindsay	1	-6/+6
2023-08-31	target/arm: Allow cpu to configure GM blocksize	Richard Henderson	1	-2/+3
2023-08-24	target/arm: Use tcg_gen_negsetcond_*	Richard Henderson	1	-13/+9
2023-07-31	target/arm: Fix MemOp for STGP	Richard Henderson	1	-3/+18
2023-07-25	arm: spelling fixes	Michael Tokarev	1	-2/+2
2023-07-08	target/arm: Demultiplex AESE and AESMC	Richard Henderson	1	-9/+4
2023-06-19	target/arm: Convert load/store tags insns to decodetree	Peter Maydell	1	-177/+165
2023-06-19	target/arm: Convert load/store single structure to decodetree	Peter Maydell	1	-108/+93
2023-06-19	target/arm: Convert load/store (multiple structures) to decodetree	Peter Maydell	1	-108/+108
2023-06-19	target/arm: Convert LDAPR/STLR (imm) to decodetree	Peter Maydell	1	-84/+44
2023-06-19	target/arm: Convert load (pointer auth) insns to decodetree	Peter Maydell	1	-67/+16
2023-06-19	target/arm: Convert atomic memory ops to decodetree	Peter Maydell	1	-98/+55
2023-06-19	target/arm: Convert LDR/STR reg+reg to decodetree	Peter Maydell	1	-87/+76
2023-06-19	target/arm: Convert LDR/STR with 12-bit immediate to decodetree	Peter Maydell	1	-88/+16
2023-06-19	target/arm: Convert ld/st reg+imm9 insns to decodetree	Peter Maydell	1	-118/+80
2023-06-19	target/arm: Convert load/store-pair to decodetree	Peter Maydell	1	-196/+188
2023-06-19	target/arm: Convert load reg (literal) group to decodetree	Peter Maydell	1	-54/+22
2023-06-19	target/arm: Convert LDXP, STXP, CASP, CAS to decodetree	Peter Maydell	1	-76/+39
2023-06-19	target/arm: Convert load/store exclusive and ordered to decodetree	Peter Maydell	1	-62/+92
2023-06-19	target/arm: Convert exception generation instructions to decodetree	Peter Maydell	1	-106/+61
2023-06-19	target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree	Peter Maydell	1	-28/+6
2023-06-19	target/arm: Convert MSR (immediate) to decodetree	Peter Maydell	1	-115/+110
2023-06-19	target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree	Peter Maydell	1	-27/+26
2023-06-19	target/arm: Convert barrier insns to decodetree	Peter Maydell	1	-53/+39
2023-06-19	target/arm: Convert hint instruction space to decodetree	Peter Maydell	1	-123/+154
2023-06-19	target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores	Peter Maydell	1	-4/+6
2023-06-19	target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode	Peter Maydell	1	-1/+1
2023-06-19	target/arm: Return correct result for LDG when ATA=0	Peter Maydell	1	-1/+5
2023-06-19	target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics	Peter Maydell	1	-2/+16
2023-06-06	target/arm: Move mte check for store-exclusive	Richard Henderson	1	-6/+36
2023-06-06	target/arm: Relax ordered/atomic alignment checks for LSE2	Richard Henderson	1	-26/+94
2023-06-06	target/arm: Add SCTLR.nAA to TBFLAG_A64	Richard Henderson	1	-0/+1
2023-06-06	target/arm: Check alignment in helper_mte_check	Richard Henderson	1	-0/+2
2023-06-06	target/arm: Pass single_memop to gen_mte_checkN	Richard Henderson	1	-12/+19