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path: root/target/arm/helper-a64.h
AgeCommit message (Expand)AuthorFilesLines
2019-03-05target/arm: Split helper_msr_i_pstate into 3Richard Henderson1-0/+3
2019-01-21target/arm: Add new_pc argument to helper_exception_returnRichard Henderson1-1/+1
2019-01-21target/arm: Move helper_exception_return to helper-a64.cRichard Henderson1-0/+2
2019-01-21target/arm: Add PAuth helpersRichard Henderson1-0/+12
2018-05-15target/arm: Implement FCMP for fp16Alex Bennée1-0/+2
2018-05-10target/arm: Implement CAS and CASPRichard Henderson1-0/+2
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée1-0/+1
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée1-0/+1
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée1-0/+2
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée1-0/+2
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée1-0/+10
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée1-0/+2
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée1-0/+2
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée1-0/+5
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée1-0/+4
2018-03-01arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée1-0/+4
2017-10-24target/arm: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-0/+4
2017-01-10target-arm: Use clrsb helperRichard Henderson1-2/+0
2017-01-10target-arm: Use clz opcodeRichard Henderson1-2/+0
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+50
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