riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-07-14	tcg: Introduce set/clear_helper_retaddr	Richard Henderson	1	-4/+4
2019-06-10	target/arm: Use env_cpu, env_archcpu	Richard Henderson	1	-2/+2
2019-03-05	target/arm: Split helper_msr_i_pstate into 3	Richard Henderson	1	-0/+30
2019-02-15	target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be	Catherine Ho	1	-2/+2
2019-01-21	target/arm: Add new_pc argument to helper_exception_return	Richard Henderson	1	-5/+5
2019-01-21	target/arm: Move helper_exception_return to helper-a64.c	Richard Henderson	1	-0/+155
2018-10-18	target/arm: Check HAVE_CMPXCHG128 at translate time	Richard Henderson	1	-12/+4
2018-10-18	target/arm: Convert to HAVE_CMPXCHG128	Richard Henderson	1	-127/+134
2018-05-31	tcg: Fix helper function vs host abi for float16	Richard Henderson	1	-17/+18
2018-05-31	target/arm: Honour FPCR.FZ in FRECPX	Peter Maydell	1	-0/+6
2018-05-17	target/arm: Remove floatX_maybe_silence_nan from conversions	Richard Henderson	1	-1/+0
2018-05-17	target/arm: Use floatX_silence_nan when we have already checked for SNaN	Richard Henderson	1	-3/+3
2018-05-15	target/arm: Implement FCMP for fp16	Alex Bennée	1	-0/+10
2018-05-10	target/arm: Implement CAS and CASP	Richard Henderson	1	-0/+43
2018-03-01	arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+13
2018-03-01	arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+29
2018-03-01	arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+32
2018-03-01	arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+22
2018-03-01	arm/translate-a64: add FP16 x2 ops for simd_indexed	Alex Bennée	1	-1/+45
2018-03-01	arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16	Alex Bennée	1	-0/+34
2018-03-01	arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16	Alex Bennée	1	-0/+24
2018-03-01	arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16	Alex Bennée	1	-0/+49
2018-03-01	arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16	Alex Bennée	1	-0/+4
2018-03-01	arm/translate-a64: implement half-precision F(MIN\|MAX)(V\|NMV)	Alex Bennée	1	-0/+18
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	1	-0/+1
2018-01-25	target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers	Richard Henderson	1	-2/+3
2018-01-11	target/arm: Fix stlxp for aarch64_be	Michael Weiser	1	-2/+5
2017-11-15	target/arm: Fix GETPC usage in do_paired_cmpxchg64_l/be	Richard Henderson	1	-8/+6
2017-11-15	target/arm: Use helper_retaddr in stxp helpers	Richard Henderson	1	-0/+6
2017-10-24	target/arm: check CF_PARALLEL instead of parallel_cpus	Emilio G. Cota	1	-6/+32
2017-01-10	target-arm: Use clrsb helper	Richard Henderson	1	-10/+0
2017-01-10	target-arm: Use clz opcode	Richard Henderson	1	-10/+0
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+559