index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
arm
/
cpu64.c
Age
Commit message (
Expand
)
Author
Files
Lines
2018-06-29
target/arm: Implement ARMv8.2-DotProd
Richard Henderson
1
-0
/
+1
2018-06-29
target/arm: Enable SVE for aarch64-linux-user
Richard Henderson
1
-0
/
+1
2018-05-10
target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only
Richard Henderson
1
-0
/
+1
2018-03-09
target/arm: Make 'any' CPU just an alias for 'max'
Peter Maydell
1
-31
/
+28
2018-03-09
target/arm: Add "-cpu max" support
Peter Maydell
1
-0
/
+21
2018-03-09
linux-user: Implement aarch64 PR_SVE_SET/GET_VL
Richard Henderson
1
-0
/
+41
2018-03-09
target/arm: Add a core count property
Alistair Francis
1
-2
/
+4
2018-03-02
target/arm: Enable ARM_FEATURE_V8_FCMA
Richard Henderson
1
-0
/
+1
2018-03-02
target/arm: Enable ARM_FEATURE_V8_RDM
Richard Henderson
1
-0
/
+1
2018-03-01
target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
Peter Maydell
1
-0
/
+1
2018-02-09
target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support
Ard Biesheuvel
1
-0
/
+4
2017-01-20
target-arm: Enable EL2 feature bit on A53 and A57
Peter Maydell
1
-0
/
+2
2017-01-20
target-arm: Add ARMCPU fields for GIC CPU i/f config
Peter Maydell
1
-0
/
+6
2016-12-20
Move target-* CPU file into a target/ folder
Thomas Huth
1
-0
/
+353