riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-06-29	target/arm: Add ID_ISAR6	Richard Henderson	1	-0/+2
2018-06-29	target/arm: Prune a57 features from max	Richard Henderson	1	-9/+0
2018-06-29	target/arm: Implement ARMv8.2-DotProd	Richard Henderson	1	-0/+1
2018-06-29	target/arm: Enable SVE for aarch64-linux-user	Richard Henderson	1	-0/+1
2018-05-10	target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only	Richard Henderson	1	-0/+1
2018-03-09	target/arm: Make 'any' CPU just an alias for 'max'	Peter Maydell	1	-31/+28
2018-03-09	target/arm: Add "-cpu max" support	Peter Maydell	1	-0/+21
2018-03-09	linux-user: Implement aarch64 PR_SVE_SET/GET_VL	Richard Henderson	1	-0/+41
2018-03-09	target/arm: Add a core count property	Alistair Francis	1	-2/+4
2018-03-02	target/arm: Enable ARM_FEATURE_V8_FCMA	Richard Henderson	1	-0/+1
2018-03-02	target/arm: Enable ARM_FEATURE_V8_RDM	Richard Henderson	1	-0/+1
2018-03-01	target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU	Peter Maydell	1	-0/+1
2018-02-09	target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support	Ard Biesheuvel	1	-0/+4
2017-01-20	target-arm: Enable EL2 feature bit on A53 and A57	Peter Maydell	1	-0/+2
2017-01-20	target-arm: Add ARMCPU fields for GIC CPU i/f config	Peter Maydell	1	-0/+6
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+353