riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-20	include: Rename sysemu/ -> system/	Philippe Mathieu-Daudé	1	-4/+4
2024-12-15	target/arm: Constify all Property	Richard Henderson	1	-3/+3
2024-12-10	arm: Replace type_register() with type_register_static()	Zhao Liu	1	-1/+1
2024-09-13	target/arm/tcg: refine cache descriptions with a wrapper	Alireza Sanaee	1	-6/+13
2024-06-04	target/arm: Replace sprintf() by snprintf()	Philippe Mathieu-Daudé	1	-2/+2
2024-05-30	target/arm: Disable SVE extensions when SVE is disabled	Marcin Juszkiewicz	1	-1/+5
2024-04-30	target/arm: Default to 1GHz cntfrq for 'max' and new CPUs	Peter Maydell	1	-0/+2
2024-02-28	gdbstub: Infer number of core registers from XML	Akihiko Odaki	1	-1/+0
2024-02-27	target/arm: Advertise Cortex-A53 erratum #843419 fix via REVIDR	Ard Biesheuvel	1	-1/+1
2023-12-19	target/arm/kvm: Have kvm_arm_sve_get_vls take a ARMCPU argument	Philippe Mathieu-Daudé	1	-1/+1
2023-10-27	target/arm: Move feature test functions to their own header	Peter Maydell	1	-0/+1
2023-10-11	hw/core/cpu: Return static value with gdb_arch_name()	Akihiko Odaki	1	-2/+2
2023-10-03	target/arm: Remove size and alignment for cpu subclasses	Richard Henderson	1	-4/+0
2023-09-08	target/arm: Implement FEAT_PACQARMA3	Richard Henderson	1	-3/+21
2023-09-08	target/arm: Don't change pauth features when changing algorithm	Richard Henderson	1	-25/+45
2023-07-25	arm: spelling fixes	Michael Tokarev	1	-1/+1
2023-07-06	target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case	Peter Maydell	1	-2/+2
2023-05-02	target/arm: Move 64-bit TCG CPUs into tcg/	Fabiano Rosas	1	-684/+3
2023-05-02	target/arm: Do not expose all -cpu max features to qtests	Fabiano Rosas	1	-3/+9
2023-05-02	target/arm: Extract TCG -cpu max code into a function	Fabiano Rosas	1	-14/+18
2023-05-02	target/arm: Remove dead code from cpu_max_set_sve_max_vq	Fabiano Rosas	1	-6/+0
2023-05-02	target/arm: Move cortex sysregs into a separate file	Fabiano Rosas	1	-0/+1
2023-04-20	target/arm: Implement FEAT_PAN3	Peter Maydell	1	-1/+1
2023-03-21	target/arm: Add Neoverse-N1 registers	Chen Baozi	1	-0/+69
2023-02-03	target/arm: Enable FEAT_FGT on '-cpu max'	Peter Maydell	1	-0/+1
2023-01-05	target/arm: cleanup cpu includes	Claudio Fontana	1	-6/+0
2022-12-15	target/arm: Report FEAT_EVT for TCG '-cpu max'	Peter Maydell	1	-0/+1
2022-12-15	target/arm: Add Cortex-A55 CPU	Timofey Kutergin	1	-0/+69
2022-10-27	target/arm: Implement FEAT_HAFDBS, dirty bit portion	Richard Henderson	1	-1/+1
2022-10-27	target/arm: Implement FEAT_HAFDBS, access flag portion	Richard Henderson	1	-0/+1
2022-10-27	target/arm: Implement FEAT_E0PD	Peter Maydell	1	-0/+1
2022-09-29	target/arm: Rearrange cpu64.c so all the CPU initfns are together	Peter Maydell	1	-356/+356
2022-09-14	target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'	Peter Maydell	1	-1/+1
2022-09-14	target/arm: Advertise FEAT_ETS for '-cpu max'	Peter Maydell	1	-0/+1
2022-09-14	target/arm: Add cortex-a35	Hao Wu	1	-0/+80
2022-07-11	target/arm: Enable SME for -cpu max	Richard Henderson	1	-0/+11
2022-07-07	target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2	Peter Maydell	1	-0/+6
2022-06-27	target/arm: Add cpu properties for SME	Richard Henderson	1	-4/+110
2022-06-27	target/arm: Unexport aarch64_add_*_properties	Richard Henderson	1	-2/+2
2022-06-27	target/arm: Generalize cpu_arm_{get, set}_default_vec_len	Richard Henderson	1	-13/+14
2022-06-27	target/arm: Generalize cpu_arm_{get,set}_vq	Richard Henderson	1	-14/+15
2022-06-27	target/arm: Create ARMVQMap	Richard Henderson	1	-11/+11
2022-06-27	target/arm: Move error for sve%d property to arm_cpu_sve_finalize	Richard Henderson	1	-8/+7
2022-06-08	target/arm: Use uint32_t instead of bitmap for sve vq's	Richard Henderson	1	-61/+56
2022-06-08	target/arm: Implement FEAT_DoubleFault	Peter Maydell	1	-2/+2
2022-06-08	target/arm: Declare support for FEAT_RASv1p1	Peter Maydell	1	-0/+1
2022-05-19	target/arm: Enable FEAT_HCX for -cpu max	Richard Henderson	1	-0/+1
2022-05-19	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	1	-0/+11
2022-05-19	hw/intc/arm_gicv3: Use correct number of priority bits for the CPU	Peter Maydell	1	-0/+6
2022-05-19	target/arm: Implement FEAT_IDST	Peter Maydell	1	-0/+1