riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-01-20	hw/arm/virt: KVM: Enable PAuth when supported by the host	Marc Zyngier	1	-0/+1
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	1	-7/+0
2021-09-21	target/arm: Add TB flag for "MVE insns not predicated"	Peter Maydell	1	-1/+3
2021-09-21	hvf: arm: Implement -cpu host	Peter Maydell	1	-0/+2
2021-09-14	target/arm: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	1	-2/+1
2021-09-13	target/arm: Take an exception if PSTATE.IL is set	Peter Maydell	1	-0/+1
2021-08-26	target/arm: Do hflags rebuild in cpsr_write()	Peter Maydell	1	-2/+8
2021-08-26	target/arm: Implement HSTR.TJDBX	Peter Maydell	1	-0/+1
2021-08-26	target/arm: Implement HSTR.TTEE	Peter Maydell	1	-0/+2
2021-08-26	target/arm/cpu: Introduce sve_vq_supported bitmap	Andrew Jones	1	-0/+4
2021-08-25	target/arm: Implement M-profile trapping on division by zero	Peter Maydell	1	-0/+1
2021-07-27	target/arm: Add sve-default-vector-length cpu property	Richard Henderson	1	-0/+5
2021-06-03	target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16	Richard Henderson	1	-0/+15
2021-06-03	target/arm: Allow board models to specify initial NS VTOR	Peter Maydell	1	-0/+2
2021-06-03	target/arm: Make FPSCR.LTPSIZE writable for MVE	Peter Maydell	1	-1/+2
2021-06-03	target/arm: Implement M-profile VPR register	Peter Maydell	1	-0/+6
2021-06-03	target/arm: Add isar feature check functions for MVE	Peter Maydell	1	-0/+22
2021-05-25	target/arm: Implement aarch32 VSUDOT, VUSDOT	Richard Henderson	1	-0/+5
2021-05-25	target/arm: Implement aarch64 SUDOT, USDOT	Richard Henderson	1	-0/+5
2021-05-25	target/arm: Implement SVE2 crypto constructive binary operations	Richard Henderson	1	-0/+5
2021-05-25	target/arm: Implement SVE2 crypto destructive binary operations	Richard Henderson	1	-0/+5
2021-05-25	target/arm: Implement SVE mixed sign dot product (indexed)	Richard Henderson	1	-0/+5
2021-05-25	target/arm: Implement SVE2 FMMLA	Stephen Long	1	-0/+10
2021-05-25	target/arm: Implement SVE2 bitwise permute	Richard Henderson	1	-0/+5
2021-05-25	target/arm: Implement SVE2 PMULLB, PMULLT	Richard Henderson	1	-0/+10
2021-05-25	target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2	Richard Henderson	1	-0/+16
2021-05-25	target/arm: Add support for FEAT_TLBIOS	Rebecca Cran	1	-0/+5
2021-05-25	target/arm: Add support for FEAT_TLBIRANGE	Rebecca Cran	1	-0/+5
2021-04-30	target/arm: Add ALIGN_MEM to TBFLAG_ANY	Richard Henderson	1	-0/+2
2021-04-30	target/arm: Move TBFLAG_ANY bits to the bottom	Richard Henderson	1	-7/+7
2021-04-30	target/arm: Move TBFLAG_AM32 bits to the top	Richard Henderson	1	-21/+21
2021-04-30	target/arm: Move mode specific TB flags to tb->cs_base	Richard Henderson	1	-21/+28
2021-04-30	target/arm: Introduce CPUARMTBFlags	Richard Henderson	1	-11/+15
2021-04-30	target/arm: Add wrapper macros for accessing tbflags	Richard Henderson	1	-1/+21
2021-04-30	target/arm: Rename TBFLAG_ANY, PSTATE_SS	Richard Henderson	1	-1/+1
2021-04-30	target/arm: Rename TBFLAG_A32, SCTLR_B	Richard Henderson	1	-1/+1
2021-04-06	Revert "target/arm: Make number of counters in PMCR follow the CPU"	Peter Maydell	1	-1/+0
2021-03-30	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	1	-0/+1
2021-03-05	target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe	Rebecca Cran	1	-1/+14
2021-02-16	linux-user/aarch64: Implement PROT_MTE	Richard Henderson	1	-0/+1
2021-02-16	linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE	Richard Henderson	1	-0/+31
2021-02-11	target/arm: Add support for FEAT_DIT, Data Independent Timing	Rebecca Cran	1	-0/+12
2021-02-11	target/arm: Fix SCR RES1 handling	Mike Nawrocki	1	-0/+5
2021-01-29	target/arm: Implement ID_PFR2	Richard Henderson	1	-0/+1
2021-01-19	target/arm: Implement SCR_EL2.EEL2	Rémi Denis-Courmont	1	-2/+6
2021-01-19	target/arm: set HPFAR_EL2.NS on secure stage 2 faults	Rémi Denis-Courmont	1	-0/+2
2021-01-19	target/arm: secure stage 2 translation regime	Rémi Denis-Courmont	1	-1/+5
2021-01-19	target/arm: add ARMv8.4-SEL2 system registers	Rémi Denis-Courmont	1	-0/+7
2021-01-19	target/arm: add MMU stage 1 for Secure EL2	Rémi Denis-Courmont	1	-14/+23
2021-01-19	target/arm: Define isar_feature function to test for presence of SEL2	Rémi Denis-Courmont	1	-0/+5