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path: root/target/arm/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2021-09-21hvf: arm: Implement PSCI handlingAlexander Graf1-2/+2
2021-09-21hvf: arm: Implement -cpu hostPeter Maydell1-4/+9
2021-09-20target/arm: Consolidate ifdef blocks in resetPeter Maydell1-12/+10
2021-09-20target/arm: Always clear exclusive monitor on resetPeter Maydell1-3/+3
2021-09-20target/arm: Don't skip M-profile reset entirely in user modePeter Maydell1-0/+19
2021-09-14target/arm: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-2/+5
2021-08-26target/arm: Avoid assertion trying to use KVM and multiple ASesPeter Maydell1-0/+23
2021-08-25target/arm: Print MVE VPR in CPU dumpsPeter Maydell1-0/+3
2021-07-27target/arm: Add sve-default-vector-length cpu propertyRichard Henderson1-2/+12
2021-07-21target/arm: Implement debug_check_breakpointRichard Henderson1-0/+1
2021-06-03target/arm: Enable BFloat16 extensionsRichard Henderson1-0/+3
2021-06-03target/arm: Allow board models to specify initial NS VTORPeter Maydell1-0/+10
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé1-2/+2
2021-05-26cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé1-0/+8
2021-05-26cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé1-1/+1
2021-05-25target/arm: Enable SVE2 and related extensionsRichard Henderson1-0/+2
2021-05-02Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth1-1/+0
2021-03-23target/arm: Make M-profile VTOR loads on reset handle memory aliasingPeter Maydell1-1/+1
2021-03-08target/arm: Restrict v7A TCG cpus to TCG accelPhilippe Mathieu-Daudé1-335/+0
2021-03-05target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé1-4/+8
2021-03-05target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé1-7/+0
2021-03-05target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPURebecca Cran1-0/+4
2021-02-16target/arm: Enable MTE for user-onlyRichard Henderson1-0/+15
2021-02-16target/arm: Use the proper TBI settings for linux-userRichard Henderson1-7/+3
2021-02-11target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPURebecca Cran1-0/+4
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-15/+26
2021-02-05cpu: move debug_check_watchpoint to tcg_opsClaudio Fontana1-2/+2
2021-02-05cpu: move adjust_watchpoint_address to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-2/+2
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-2/+2
2021-02-05cpu: Move debug_excp_handler to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost1-1/+3
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont1-1/+1
2021-01-19target/arm: remove redundant testsRémi Denis-Courmont1-4/+4
2021-01-19target/arm: Add cpu properties to control pauthRichard Henderson1-0/+13
2021-01-08target/arm: Remove timer_del()/timer_deinit() before timer_free()Peter Maydell1-2/+0
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson1-1/+2
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell1-0/+3
2020-12-10target/arm: Don't clobber ID_PFR1.Security on M-profile coresPeter Maydell1-1/+1
2020-10-20target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extensionPeter Maydell1-0/+9
2020-10-20target/arm: Fix has_vfp/has_neon ID reg squashing for M-profilePeter Maydell1-12/+19
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