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target-xtensa
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Author
Files
Lines
2013-10-15
target-xtensa: add in_asm logging
Max Filippov
1
-0
/
+8
2013-10-10
tcg: Move helper registration into tcg_context_init
Richard Henderson
1
-2
/
+0
2013-09-02
target: Include softmmu_exec.h where forgotten
Richard Henderson
1
-0
/
+1
2013-09-02
tcg: Change tcg_gen_exit_tb argument to uintptr_t
Richard Henderson
1
-1
/
+1
2013-08-22
aio / timers: Switch entire codebase to the new timer API
Alex Bligh
1
-1
/
+1
2013-08-05
Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging
Anthony Liguori
3
-23
/
+53
2013-07-29
target-xtensa: check register window inline
Max Filippov
1
-8
/
+25
2013-07-29
target-xtensa: don't generate dead code to access invalid SRs
Max Filippov
1
-13
/
+18
2013-07-29
target-xtensa: avoid double-stopping at breakpoints
Max Filippov
3
-2
/
+8
2013-07-29
target-xtensa: add fallthrough markers
Max Filippov
1
-0
/
+2
2013-07-29
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Andreas Färber
1
-0
/
+2
2013-07-27
cpu: Introduce CPUClass::gdb_{read,write}_register()
Andreas Färber
4
-2
/
+14
2013-07-27
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
Andreas Färber
1
-6
/
+8
2013-07-27
target-xtensa: Move cpu_gdb_{read,write}_register()
Andreas Färber
1
-0
/
+100
2013-07-26
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
Andreas Färber
2
-0
/
+11
2013-07-26
target-xtensa: Introduce XtensaCPU subclasses
Andreas Färber
3
-12
/
+47
2013-07-23
exec: Change cpu_memory_rw_debug() argument to CPUState
Andreas Färber
1
-5
/
+5
2013-07-23
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Andreas Färber
4
-5
/
+10
2013-07-23
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Andreas Färber
1
-3
/
+4
2013-07-23
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Andreas Färber
1
-5
/
+0
2013-07-23
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
Andreas Färber
1
-0
/
+8
2013-07-09
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
Andreas Färber
1
-4
/
+5
2013-07-09
target-xtensa: gen_intermediate_code_internal() should be inlined
Andreas Färber
1
-2
/
+3
2013-07-09
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
Andreas Färber
1
-1
/
+1
2013-06-28
cpu: Change qemu_init_vcpu() argument to CPUState
Andreas Färber
1
-3
/
+0
2013-06-28
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Andreas Färber
4
-3
/
+10
2013-03-12
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
Andreas Färber
4
-2
/
+7
2013-03-12
cpu: Move halted and interrupt_request fields to CPUState
Andreas Färber
1
-1
/
+4
2013-03-03
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
Peter Maydell
1
-2
/
+2
2013-03-03
cpu: Introduce ENV_OFFSET macros
Andreas Färber
1
-0
/
+1
2013-02-23
target-xtensa: Use add2/sub2 for mac
Richard Henderson
1
-16
/
+13
2013-02-23
target-xtensa: Use mul*2 for mul*hi
Richard Henderson
1
-14
/
+6
2013-02-16
cpu: Add CPUArchState pointer to CPUState
Andreas Färber
1
-0
/
+2
2013-02-16
target-xtensa: Move TCG initialization to XtensaCPU initfn
Andreas Färber
3
-13
/
+9
2013-02-16
target-xtensa: Introduce QOM realizefn for XtensaCPU
Andreas Färber
3
-1
/
+18
2013-02-01
target-xtensa: Mark as unmigratable
Andreas Färber
3
-39
/
+9
2012-12-22
target-xtensa: fix search_pc for the last TB opcode
Max Filippov
1
-1
/
+5
2012-12-19
softmmu: move include files to include/sysemu/
Paolo Bonzini
1
-1
/
+1
2012-12-19
misc: move include files to include/qemu/
Paolo Bonzini
7
-7
/
+7
2012-12-19
qom: move include files to include/qom/
Paolo Bonzini
1
-1
/
+1
2012-12-19
exec: move include files to include/exec/
Paolo Bonzini
8
-19
/
+19
2012-12-19
build: kill libdis, move disassemblers to disas/
Paolo Bonzini
1
-1
/
+1
2012-12-16
exec: refactor cpu_restore_state
Blue Swirl
1
-12
/
+2
2012-12-15
target-xtensa: fix ITLB/DTLB page protection flags
Max Filippov
1
-1
/
+2
2012-12-08
target-xtensa: use movcond where possible
Max Filippov
1
-50
/
+42
2012-12-08
target-xtensa: implement MISC SR
Max Filippov
3
-0
/
+6
2012-12-08
target-xtensa: better control rsr/wsr/xsr access to SRs
Max Filippov
1
-19
/
+30
2012-12-08
target-xtensa: restrict available SRs by enabled options
Max Filippov
3
-105
/
+130
2012-12-08
target-xtensa: implement CACHEATTR SR
Max Filippov
5
-1
/
+25
2012-12-08
target-xtensa: implement ATOMCTL SR
Max Filippov
7
-14
/
+131
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