aboutsummaryrefslogtreecommitdiff
path: root/target-xtensa
AgeCommit message (Expand)AuthorFilesLines
2012-08-09Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemuBlue Swirl1-7/+1
2012-08-09target-xtensa: make default CPU depend on target endiannessMax Filippov1-0/+6
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov1-2/+14
2012-06-25target-xtensa: drop usage of prev_debug_excp_handlerIgor Mammedov1-7/+1
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov4-154/+151
2012-06-10target-xtensa: add attributes to helper functionsMax Filippov1-8/+8
2012-06-10target-xtensa: remove unnecessary include of dyngen-exec.hPeter Portante1-1/+0
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov1-0/+2
2012-06-09target-xtensa: control page table lookup explicitlyMax Filippov1-5/+5
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov3-27/+35
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov2-4/+14
2012-06-09target-xtensa: update EXCVADDR in case of page table lookupMax Filippov1-0/+1
2012-06-09target-xtensa: flush TLB page for new MMU mappingMax Filippov1-0/+1
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-0/+3
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2-0/+228
2012-06-04Kill off cpu_state_reset()Andreas Färber1-5/+0
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber3-6/+16
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov1-1/+1
2012-04-15target-xtensa: add license to core-fsf.cMax Filippov1-0/+27
2012-04-15target-xtensa: add license to core-dc232b.cMax Filippov1-0/+27
2012-04-15target-xtensa: add dc233c coreMax Filippov3-0/+674
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov2-11/+20
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-5/+4
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber2-1/+9
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber3-14/+14
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber4-1/+153
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova3-4/+4
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber4-68/+68
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber1-1/+1
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl3-3/+0
2012-02-28target-xtensa: Clean includesStefan Weil3-3/+0
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov3-0/+7
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov5-0/+147
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2-1/+54
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov5-3/+119
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2-0/+21
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov1-1/+2
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov2-0/+68
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov1-2/+16
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov2-2/+2
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov1-1/+6
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov1-0/+6
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov1-1/+1
2011-10-16target-xtensa: add fsf coreMax Filippov2-0/+383
2011-10-16target-xtensa: add dc232b coreMax Filippov3-0/+712
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov3-13/+554
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov1-0/+3
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov3-860/+2
generated by cgit v1.1 at 2024-11-19 00:44:25 +0000