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path: root/target-xtensa/translate.c
AgeCommit message (Expand)AuthorFilesLines
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov1-2/+7
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov1-0/+27
2014-02-24target-xtensa: add basic checks to dcache opcodesMax Filippov1-0/+38
2014-02-24target-xtensa: add RRRI4 opcode format fieldsMax Filippov1-0/+9
2013-10-15target-xtensa: add in_asm loggingMax Filippov1-0/+8
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-2/+0
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-07-29target-xtensa: check register window inlineMax Filippov1-8/+25
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov1-13/+18
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov1-2/+1
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-09target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber1-4/+5
2013-07-09target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber1-2/+3
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-2/+4
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson1-16/+13
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson1-14/+6
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov1-1/+5
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-08target-xtensa: use movcond where possibleMax Filippov1-50/+42
2012-12-08target-xtensa: implement MISC SRMax Filippov1-0/+4
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov1-19/+30
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov1-104/+126
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov1-0/+1
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov1-0/+13
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-10target-xtensa: avoid using cpu_single_envBlue Swirl1-5/+5
2012-10-06target-xtensa: de-optimize EXTUIAurelien Jarno1-20/+2
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov1-0/+38
2012-09-22target-xtensa: implement FP1 groupMax Filippov1-1/+80
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov1-0/+48
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov1-1/+60
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov1-4/+54
2012-09-22target-xtensa: add FP registersMax Filippov1-7/+45
2012-09-21target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov1-1/+3
2012-09-21target-xtensa: fix extui shift amountMax Filippov1-3/+21
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov1-2/+14
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov1-30/+34
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov1-0/+2
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov1-1/+1
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov1-0/+2
generated by cgit v1.1 at 2024-11-01 02:32:38 +0000