index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-tricore
/
tricore-opcodes.h
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-23
target-tricore: Add FPU infrastructure
Bastian Koppelmann
1
-0
/
+18
2015-05-22
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+2
2015-05-22
target-tricore: add FRET instructions of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+2
2015-05-22
target-tricore: add FCALL instructions of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+3
2015-05-22
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+1
2015-05-22
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
Bastian Koppelmann
1
-0
/
+1
2015-05-22
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
Bastian Koppelmann
1
-0
/
+5
2015-05-22
target-tricore: add CMPSWP instructions of the v1.6.1 ISA
Bastian Koppelmann
1
-0
/
+5
2015-05-11
target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
Bastian Koppelmann
1
-1
/
+1
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...
Bastian Koppelmann
1
-2
/
+2
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...
Bastian Koppelmann
1
-2
/
+2
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...
Bastian Koppelmann
1
-24
/
+24
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...
Bastian Koppelmann
1
-4
/
+4
2015-03-03
target-tricore: Add instructions of RRR2 opcode format
Bastian Koppelmann
1
-1
/
+1
2015-01-27
target-tricore: Add instructions of RRR opcode format
Bastian Koppelmann
1
-1
/
+1
2015-01-15
target-tricore: Fix new typos
Stefan Weil
1
-2
/
+2
2014-12-21
target-tricore: Fix MFCR/MTCR insn and B format offset.
Bastian Koppelmann
1
-0
/
+2
2014-12-21
target-tricore: Add missing 1.6 insn of BOL opcode format
Bastian Koppelmann
1
-0
/
+6
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...
Bastian Koppelmann
1
-1
/
+1
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...
Bastian Koppelmann
1
-2
/
+2
2014-12-21
target-tricore: add missing 64-bit MOV in RLC format
Alex Zuepke
1
-0
/
+1
2014-12-21
target-tricore: typo in BOL format
Alex Zuepke
1
-1
/
+1
2014-12-21
target-tricore: fix offset masking in BOL format
Alex Zuepke
1
-1
/
+1
2014-12-10
target-tricore: Add instructions of RCR opcode format
Bastian Koppelmann
1
-1
/
+2
2014-12-10
target-tricore: Add instructions of RLC opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of RC opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of BRR opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of BRN opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of BRC opcode format
Bastian Koppelmann
1
-2
/
+4
2014-12-10
target-tricore: Add instructions of BOL opcode format
Bastian Koppelmann
1
-1
/
+3
2014-10-20
target-tricore: Add instructions of BO opcode format
Bastian Koppelmann
1
-0
/
+2
2014-10-20
target-tricore: Cleanup and Bugfixes
Bastian Koppelmann
1
-1
/
+1
2014-09-01
target-tricore: Add masks and opcodes for decoding
Bastian Koppelmann
1
-0
/
+1406