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AgeCommit message (Expand)AuthorFilesLines
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-2/+2
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-01-29tilegx: Clean up includesPeter Maydell4-0/+4
2015-10-22target-tilegx: Implement prefetch instructions in pipe y2Chen Gang1-8/+14
2015-10-09qdev: Protect device-list-properties against broken devicesMarkus Armbruster1-0/+7
2015-10-08Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell2-45/+14
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-37/+4
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+3
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-0/+3
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson1-1/+0
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-1/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+2
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-10-07target-tilegx: Support iret instruction and related special registersChen Gang4-1/+38
2015-10-07target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEM...Chen Gang1-17/+24
2015-10-07target-tilegx: Implement v2mults instructionChen Gang3-0/+20
2015-10-07target-tilegx: Implement v?int_* instructions.Chen Gang3-0/+67
2015-10-07target-tilegx: Implement v2sh* instructionsChen Gang1-1/+17
2015-10-07target-tilegx: Handle nofault prefetch instructionsRichard Henderson1-14/+26
2015-10-07target-tilegx: Fix a typo for mnemonic about "ld_add"Chen Gang1-1/+1
2015-10-07target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGVRichard Henderson2-3/+7
2015-10-07target-tilegx: Decode ill pseudo-instructionsChen Gang2-15/+71
2015-10-07target-tilegx: Let x1 pipe process bpt instruction onlyChen Gang1-1/+7
2015-10-07target-tilegx: Implement complex multiply instructionsRichard Henderson3-1/+73
2015-10-07target-tilegx: Implement table index instructionsRichard Henderson1-0/+15
2015-10-07target-tilegx: Implement crc instructionsRichard Henderson3-1/+28
2015-10-07target-tilegx: Implement v1multu instructionChen Gang3-0/+18
2015-10-07target-tilegx: Implement v*add and v*sub instructionsChen Gang1-21/+116
2015-10-07target-tilegx: Implement v*shl, v*shru, and v*shrs instructionsChen Gang3-0/+73
2015-10-07target-tilegx: Tidy simd_helper.cRichard Henderson1-4/+7
2015-09-15target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson4-2/+76
2015-09-15target-tilegx: Handle v1shli, v1shruiRichard Henderson1-0/+14
2015-09-15target-tilegx: Handle v4int_l/hRichard Henderson1-0/+8
2015-09-15target-tilegx: Handle atomic instructionsRichard Henderson2-2/+82
2015-09-15target-tilegx: Handle mtspr, mfsprRichard Henderson1-3/+73
2015-09-15target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson1-0/+51
2015-09-15target-tilegx: Handle mask instructionsRichard Henderson1-2/+9
2015-09-15target-tilegx: Handle scalar multiply instructionsRichard Henderson1-0/+112
2015-09-15target-tilegx: Handle conditional move instructionsRichard Henderson1-1/+8
2015-09-15target-tilegx: Handle shift instructionsRichard Henderson1-2/+54
2015-09-15target-tilegx: Handle bitfield instructionsRichard Henderson1-0/+74
2015-09-15target-tilegx: Implement system and memory management instructionsRichard Henderson1-23/+54
2015-09-15target-tilegx: Handle comparison instructionsRichard Henderson1-6/+33
2015-09-15target-tilegx: Handle conditional branch instructionsRichard Henderson1-13/+38
2015-09-15target-tilegx: Handle unconditional jump instructionsRichard Henderson1-17/+41
2015-09-15target-tilegx: Handle post-increment load and store instructionsRichard Henderson1-8/+86
2015-09-15target-tilegx: Handle basic load and store instructionsRichard Henderson1-15/+115
2015-09-15target-tilegx: Handle most bit manipulation instructionsRichard Henderson3-1/+79
2015-09-15target-tilegx: Handle arithmetic instructionsRichard Henderson1-6/+90
2015-09-15target-tilegx: Handle simple logical operationsRichard Henderson1-3/+96
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