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path: root/target-sparc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
2009-06-06Use correct type for SPARC cpu_cc_opPaul Brook1-1/+2
2009-05-10Convert mulsccBlue Swirl1-131/+2
2009-05-10Convert udiv/sdivBlue Swirl1-19/+6
2009-05-10Convert tagged opsBlue Swirl1-129/+8
2009-05-10Convert subxBlue Swirl1-31/+6
2009-05-10Convert subBlue Swirl1-37/+11
2009-05-10Convert logical operations and umul/smulBlue Swirl1-24/+24
2009-05-10Convert addxBlue Swirl1-31/+6
2009-05-10Convert addBlue Swirl1-21/+6
2009-05-10Use dynamical computation for condition codesBlue Swirl1-24/+108
2009-05-03Optimize cmp x, 0 caseBlue Swirl1-14/+19
2009-05-03ReindentBlue Swirl1-319/+312
2009-05-02Improve instruction name comments for easier searchingBlue Swirl1-44/+44
2009-05-02Optimize operations with immediate parametersBlue Swirl1-52/+200
2009-05-02Fix Sparc64 sign extension problemsBlue Swirl1-32/+36
2009-04-05Add new command line option -singlestep for tcg single stepping.aurel321-1/+1
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir11-20/+0
2009-01-15global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori1-2/+2
2009-01-15Convert references to logfile/loglevel to use qemu_log*() macrosaliguori1-9/+6
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-11-25Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori1-2/+2
2008-11-18Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori1-3/+4
2008-11-17TCG variable type checking.pbrook1-523/+521
2008-11-09Use TCG not opblueswir11-14/+12
2008-11-09Use andc, orc, nor and nandblueswir11-52/+36
2008-11-01Fix TCGv size mismatchesblueswir11-19/+21
2008-09-26Implement UA2005 hypervisor trapsblueswir11-2/+23
2008-09-22Add software and timer interrupt supportblueswir11-5/+29
2008-09-21Use the new concat_tl_i64 op for std and stdablueswir11-18/+6
2008-09-21Use the new concat_i32_i64 op for std and stdablueswir11-16/+20
2008-09-13Fix mulscc with high bits set in either src1 or src2blueswir11-2/+3
2008-09-11Write zeros to high bits of y, based on patch by Vince Weaverblueswir11-2/+4
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir11-35/+16
2008-09-10Partially convert float128 conversion ops to TCGblueswir11-8/+6
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir11-46/+65
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir11-76/+38
2008-09-10Convert basic float32 ops to TCGblueswir11-150/+247
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir11-8/+23
2008-09-06Fix a typo in fpsub32blueswir11-1/+1
2008-09-06Convert most env fields to TCG registersblueswir11-95/+91
2008-09-06Silence gcc warning about constant overflowblueswir11-2/+2
2008-09-02Fix sign extension problems with smul and umul (Vince Weaver)blueswir11-4/+4
2008-09-01Fix y register loads and storesblueswir11-18/+16
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir11-4/+2
2008-08-21Fix wrwim masking (Luis Pureza)blueswir11-0/+3
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir11-10/+7
2008-08-17Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir11-5/+8
2008-08-06Fix Sparc64 shiftsblueswir11-5/+3
2008-08-06Fix offset handling for ASI loads and stores (Vince Weaver)blueswir11-3/+1
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