riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2014-03-13	cputlb: Change tlb_flush() argument to CPUState	Andreas Färber	1	-1/+2
2012-12-19	misc: move include files to include/qemu/	Paolo Bonzini	1	-1/+1
2012-03-14	target-sparc: Don't overuse CPUState	Andreas Färber	1	-2/+2
2011-10-26	target-sparc: Change fpr representation to doubles.	Richard Henderson	1	-14/+6
2011-06-26	Remove exec-all.h include directives	Blue Swirl	1	-1/+1
2011-06-26	Sparc32: dummy implementation of MXCC MMU breakpoint registers	Blue Swirl	1	-0/+26
2010-05-09	sparc: Fix lazy flag calculation on interrupts, refactor	Blue Swirl	1	-2/+2
2010-01-27	sparc64: reimplement tick timers v4	Igor V. Kovalenko	1	-7/+7
2009-08-04	Sparc64: replace tsptr with helper routine	Igor Kovalenko	1	-1/+0
2009-07-27	sparc64 name mmu registers and general cleanup	Igor Kovalenko	1	-8/+8
2009-05-21	Convert machine registration to use module init functions	Anthony Liguori	1	-22/+0
2008-12-13	Remove unnecessary trailing newlines	blueswir1	1	-2/+0
2008-09-26	Add a generic Niagara machine	blueswir1	1	-0/+1
2008-08-01	Handle wrapped registers correctly when saving	blueswir1	1	-1/+11
2008-07-25	Make MAXTL dynamic, bounds check tl when indexing	blueswir1	1	-5/+5
2008-07-24	Sparc32: save/load all MMU registers, Sparc64: add CPU save/load	blueswir1	1	-3/+109
2008-07-22	Add T1 and T2 CPUs, add a Sun4v machine	blueswir1	1	-0/+1
2008-06-07	Allow NWINDOWS selection (CPU feature with model specific defaults)	blueswir1	1	-2/+6
2008-05-04	remove target ifdefs from vl.c	aurel32	1	-0/+102