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target-sparc
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cpu.h
Age
Commit message (
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Author
Files
Lines
2011-09-10
Gdbstub: Fix back-trace on SPARC32
Fabien Chouteau
1
-0
/
+7
2011-08-07
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Blue Swirl
1
-1
/
+1
2011-07-21
SPARC64: implement addtional MMU faults related to nonfaulting load
Tsuneo Saito
1
-0
/
+4
2011-07-21
SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault()
Tsuneo Saito
1
-0
/
+2
2011-07-21
SPARC64: SFSR cleanup and fix
Tsuneo Saito
1
-0
/
+22
2011-07-21
SPARC64: TTE bits cleanup
Tsuneo Saito
1
-0
/
+7
2011-07-20
Fix unassigned memory access handling
Blue Swirl
1
-2
/
+2
2011-07-14
Sparc: fix FPU and AM enable checks for translation
Blue Swirl
1
-16
/
+33
2011-06-26
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Blue Swirl
1
-0
/
+14
2011-06-26
sparc: move do_interrupt to helper.c
Blue Swirl
1
-0
/
+4
2011-06-26
Sparc32: dummy implementation of MXCC MMU breakpoint registers
Blue Swirl
1
-1
/
+3
2011-02-01
SPARC: Fix Leon3 cache control
Fabien Chouteau
1
-2
/
+6
2011-01-24
SPARC: Add asr17 register support
Fabien Chouteau
1
-0
/
+1
2011-01-24
SPARC: Emulation of Leon3
Fabien Chouteau
1
-14
/
+23
2010-12-19
Sparc: implement monitor command 'info tlb'
Blue Swirl
1
-1
/
+1
2010-12-04
target-sparc: Use fprintf_function (format checking)
Stefan Weil
1
-2
/
+2
2010-12-03
target-sparc: remove unused functions cpu_lock(), cpu_unlock()
Peter Maydell
1
-2
/
+0
2010-07-03
remove exec-all.h inclusion from cpu.h
Paolo Bonzini
1
-1
/
+0
2010-07-03
move cpu_pc_from_tb to target-*/exec.h
Paolo Bonzini
1
-6
/
+0
2010-05-22
sparc64: fix mmu context at trap levels above zero
Igor V. Kovalenko
1
-4
/
+10
2010-05-22
sparc64: fix pstate privilege bits
Igor V. Kovalenko
1
-18
/
+43
2010-05-16
sparc64: fix TT_WOTHER value
Igor V. Kovalenko
1
-1
/
+1
2010-05-09
sparc: Fix lazy flag calculation on interrupts, refactor
Blue Swirl
1
-90
/
+12
2010-05-06
sparc64: handle asi referencing nucleus and secondary MMU contexts
Igor V. Kovalenko
1
-1
/
+12
2010-05-06
sparc64: implement global translation table entries v1
Igor V. Kovalenko
1
-0
/
+18
2010-04-17
target-sparc: Fix TARGET_{PHYS,VIRT}_ADDR_SPACE_BITS.
Richard Henderson
1
-6
/
+6
2010-03-12
Target specific usermode cleanup
Paul Brook
1
-0
/
+2
2010-03-12
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Richard Henderson
1
-0
/
+8
2010-01-27
sparc64: reimplement tick timers v4
Igor V. Kovalenko
1
-6
/
+22
2010-01-27
sparc64: correct write extra bits to cwp
Igor V. Kovalenko
1
-1
/
+1
2010-01-08
sparc64: interrupt trap handling
Igor V. Kovalenko
1
-0
/
+10
2010-01-08
sparc64: move cpu_interrupts_enabled to cpu.h
Igor V. Kovalenko
1
-0
/
+13
2010-01-08
sparc64: add macros to deal with softint and timer interrupt
Igor V. Kovalenko
1
-0
/
+4
2009-12-05
Sparc64: handle MMU global bit and nucleus context
Blue Swirl
1
-0
/
+2
2009-10-01
Revert "Get rid of _t suffix"
Anthony Liguori
1
-1
/
+1
2009-10-01
Get rid of _t suffix
malc
1
-1
/
+1
2009-08-24
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
Nathan Froyd
1
-0
/
+1
2009-08-22
sparc32 remove an unnecessary cpu irq set
Blue Swirl
1
-35
/
+30
2009-08-04
Sparc64: replace tsptr with helper routine
Igor Kovalenko
1
-1
/
+2
2009-07-27
sparc64 really implement itlb/dtlb automatic replacement writes
Igor Kovalenko
1
-0
/
+11
2009-07-27
sparc64 name mmu registers and general cleanup
Igor Kovalenko
1
-6
/
+32
2009-07-12
sparc64: trap handling corrections
Igor Kovalenko
1
-6
/
+34
2009-05-19
Hardware convenience library
Paul Brook
1
-2
/
+0
2009-05-10
Use dynamical computation for condition codes
Blue Swirl
1
-0
/
+24
2009-03-07
The _exit syscall is used for both thread termination in NPTL applications,
pbrook
1
-1
/
+2
2008-12-23
Add SuperSPARC MMU breakpoint registers (Robert Reif)
blueswir1
1
-0
/
+1
2008-12-23
Better SuperSPARC emulation (Robert Reif)
blueswir1
1
-0
/
+1
2008-12-23
Implement tick interrupt disable bits
blueswir1
1
-1
/
+2
2008-11-18
Refactor translation block CPU state handling (Jan Kiszka)
aliguori
1
-0
/
+16
2008-11-18
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
aliguori
1
-5
/
+7
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