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2014-02-20Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-peter' ↵Peter Maydell1-19/+19
into staging QOM infrastructure fixes and device conversions * QTest cleanups and test cases for PCI NICs * NAND fix for "info qtree" * Cleanup and extension of QOM machine tests * IndustryPack test cases and conversion to QOM realize * I2C cleanups * Cleanups of legacy qdev properties # gpg: Signature made Mon 17 Feb 2014 22:15:37 GMT using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" * remotes/afaerber/tags/qom-devices-for-peter: (49 commits) qtest: Include system headers before user headers qapi: Refine human printing of sizes qdev: Use QAPI type names for properties qdev: Add enum property types to QAPI schema block: Handle "rechs" and "large" translation options qdev: Remove hex8/32/64 property types qdev: Remove most legacy printers qdev: Use human mode in "info qtree" qapi: Add human mode to StringOutputVisitor qdev: Inline qdev_prop_parse() qdev: Legacy properties are just strings qdev: Legacy properties are now read-only qdev: Remove legacy parsers for hex8/32/64 qdev: Sizes are now parsed by StringInputVisitor qapi: Add size parser to StringInputVisitor qtest: Don't segfault with invalid -qtest option ipack: Move IndustryPack out of hw/char/ ipoctal232: QOM parent field cleanup ipack: QOM parent field cleanup for IPackDevice ipack: QOM parent field cleanup for IPackBus ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-14PPC: KVM: Add missing address space to ldl_phys helperAlexander Graf1-1/+1
We now have to pass an address space to our _phys helpers. During the transition apparently the EPR exit path missed out, so let's put it there. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-13target-ppc: Make ppc40x CPUs available in ppcembAndreas Färber1-19/+19
Not only 44x CPUs (BookE) but also 40x CPUs can run with 1k page size. Move the criteria to a central inline function to avoid repetition and #ifdef'fery. Update qom-test to no longer exempt them. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias1-2/+4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stq_*_phys input an AddressSpaceEdgar E. Iglesias1-2/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias1-2/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias2-3/+7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2013-12-22PPC: Fix compilation with TCG debugAlexander Graf1-62/+81
The recent VSX patches broken compilation of QEMU when configurated with --enable-debug, as it was treating "target long" TCG variables as "i64" which is not true for 32bit targets. This patch fixes all the places that the compiler has found to use the correct variable type and if necessary manually cast. Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-20PPC: Add VSX to hflagsAlexander Graf1-1/+1
We generate different code depending on whether MSR_VSX is set or clear, so it needs to be part of our hflags too which indicate whether we're still in the same translation block cache bucket. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxsldwiTom Musta1-0/+62
This patch adds the VSX Shift Left Double by Word Immediate (xxsldwi) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxspltwTom Musta1-0/+31
This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxselTom Musta1-0/+76
This patch adds the VSX Select (xxsel) instruction. The xxsel instruction has four VSR operands. Thus the xC instruction decoder is added. The xxsel instruction is massively overloaded in the opcode table since only bits 26 and 27 are opcode bits. This overloading is done in matrix fashion with two macros (GEN_XXSEL_ROW and GEN_XX_SEL). V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation using tcg_gen_andc_i64. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxmrgh/xxmrglTom Musta1-0/+41
This patch adds the VSX Merge High Word and VSX Merge Low Word instructions. V2: Now implemented using deposit (per Richard Henderson's comment) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add Power7 VSX Logical InstructionsTom Musta1-0/+29
This patch adds the VSX logical instructions that are defined by the Version 2.06 Power ISA (aka Power7): - xxland - xxlandc - xxlor - xxlxor - xxlnor Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Vector Move InstructionsTom Musta1-0/+71
This patch adds the vector move instructions: - xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision - xvabssp - Vector Absolute Value Single-Precision - xvnabssp - Vector Negative Absolute Value Single-Precision - xvnegsp - Vector Negate Single-Precision - xvcpsgnsp - Vector Copy Sign Single-Precision V3: Per Paolo Bonzini's suggestion, used a temporary for the sign mask and andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Scalar Move InstructionsTom Musta1-0/+70
This patch adds the VSX scalar move instructions: - xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision) A common generator macro (VSX_SCALAR_MOVE) is added since these instructions vary only slightly from each other. Macros to support VSX XX2 and XX3 form opcodes are also added. These macros handle the overloading of "opcode 2" space (instruction bits 26:30) caused by AX and BX bits (29 and 30, respectively). V3: Per feedback from Paolo Bonzini, moved the sign mask into a temporary and used andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: move POWER7+ to a separate familyAlexey Kardashevskiy3-1/+41
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvw4xTom Musta1-0/+28
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxsdxTom Musta1-0/+15
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvw4xTom Musta1-0/+29
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x) instruction. V2: changed to use deposit_i64 per Richard Henderson's review. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvdsxTom Musta1-0/+16
This patch adds the Load VSX Vector Doubleword & Splat Indexed (lxvdsx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxsdxTom Musta1-0/+16
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) instruction. The lower 8 bytes of the target register are undefined; this implementation leaves those bytes unaltered. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxpermdiTom Musta1-1/+40
This patch adds the xxpermdi instruction. The instruction uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX and BX). This results in overloading of the opcode table with aliases, which can be seen in the GEN_XX3FORM_DM macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvd2xTom Musta1-0/+18
This patch adds the stxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvd2xTom Musta1-0/+18
This patch adds the lxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSR to Global RegistersTom Musta1-0/+27
This patch adds VSX VSRs to the the list of global register indices. More specifically, it adds the lower halves of the first 32 VSRs to the list of global register indices. The upper halves of the first 32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs are already defined via the cpu_avrh[] and cpu_avrl[] arrays. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Instruction DecodersTom Musta1-0/+11
This patch adds decoders for the VSX fields XT, XS, XA, XB and DM. The first four are split fields and a general helper for these types of fields is also added. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add MSR VSX and Associated ExceptionTom Musta4-2/+18
This patch adds support for the VSX bit of the PowerPC Machine State Register (MSR) as well as the corresponding VSX Unavailable exception. The VSX bit is added to the defined bits masks of the Power7 and Power8 CPU models. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Declare and Enable VSXTom Musta2-3/+8
This patch adds the flag POWERPC_FLAG_VSX to the list of defined flags and also adds this flag to the list of supported features of the Power7 and Power8 CPUs. Additionally, the VSX instructions are added to the list of TCG-enabled instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy5-0/+56
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and a CPU version in lower 16 bits. Since there is no significant change in behavior between versions, there is no point to add every single CPU version in QEMU's CPU list. Also, new CPU versions of already supported CPU won't break the existing code. This adds PVR value/mask support for KVM, i.e. for -cpu host option. As CPU family class name for POWER7 is "POWER7-family", there is no need to touch aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: add stubs for KVM breakpointsGreg Kurz1-0/+28
The latest update to v3.13-rc3 (bf63839f) breaks the ppc build with KVM: kvm-all.o: In function `kvm_update_guest_debug': kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug' kvm-all.o: In function `kvm_insert_breakpoint': kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint' kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint' kvm-all.o: In function `kvm_remove_breakpoint': kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint' kvm-all.o: In function `kvm_remove_all_breakpoints': kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints' We need stubs until something gets implemented. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25spapr: Use DeviceClass::fw_name for device tree CPU nodeAndreas Färber1-0/+2
Instead of relying on cpu_model, obtain the device tree node label per CPU. Use DeviceClass::fw_name as source. Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN". As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name, obsoleting sPAPREnvironment::cpu_model, and spapr_create_fdt_skel() can drop its cpu_model argument. Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Fill in OpenFirmware names for some PowerPCCPU familiesAndreas Färber1-0/+3
Set the expected values for POWER7, POWER7+, POWER8 and POWER5+. Note that POWER5+ and POWER7+ are intentionally lacking the '+', so the lack of a POWER7P family constitutes no problem. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: dump-guest-memory supportAneesh Kumar K.V4-2/+262
This patch add support for dumping guest memory using dump-guest-memory monitor command. Before patch: (qemu) dump-guest-memory testcrash this feature or command is not currently supported (qemu) After patch: (qemu) dump-guest-memory testcrash (qemu) crash was able to read the file crash> bt PID: 0 TASK: c000000000c0d0d0 CPU: 0 COMMAND: "swapper/0" R0: 0000000028000084 R1: c000000000cafa50 R2: c000000000cb05b0 R3: 0000000000000000 R4: c000000000bc4cb0 R5: 0000000000000000 R6: 001efe93b8000000 R7: 0000000000000000 R8: 0000000000000000 R9: b000000000001032 R10: 0000000000000001 R11: 0001eb2117e00d55 .... ... NOTE: Currently crash tools doesn't look at ELF notes in the dump on ppc64. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Use #define for max slb entriesAneesh Kumar K.V3-4/+5
Instead of opencoding 64 use MAX_SLB_ENTRIES. We don't update the kernel header here. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Update slb array with correct index values.Aneesh Kumar K.V1-2/+15
Without this, a value of rb=0 and rs=0 results in replacing the 0th index. This can be observed when using gdb remote debugging support. (gdb) x/10i do_fork 0xc000000000085330 <do_fork>: Cannot access memory at address 0xc000000000085330 (gdb) This is because when we do the slb sync via kvm_cpu_synchronize_state, we overwrite the slb entry (0th entry) for 0xc000000000085330 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Add helper for KVM_PPC_RTAS_DEFINE_TOKENDavid Gibson2-0/+21
Recent PowerKVM allows the kernel to intercept some RTAS calls from the guest directly. This is used to implement the more efficient in-kernel XICS for example. qemu is still responsible for assigning the RTAS token numbers however, and needs to tell the kernel which RTAS function name is assigned to a given token value. This patch adds a convenience wrapper for the KVM_PPC_RTAS_DEFINE_TOKEN ioctl() which is used for this purpose. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25PPC: Fix L2CR write accessesAlexander Graf1-12/+17
Commit 2345f1c01 was supposed to render L2CR writes into noops. Instead, it made them illegal instruction traps which apparently didn't confuse XNU, but can easily confuse other OSs. Fix it up by actually doing nothing when we write to L2CR. Reported-by: Julio Guerra <guerr@julio.in> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Julio Guerra <guerr@julio.in>
2013-10-25target-ppc: Little Endian Correction to Load/Store Vector ElementTom Musta1-0/+2
The Load Vector Element (lve*x) and Store Vector Element (stve*x) instructions not only byte-swap in Little Endian mode, they also invert the element that is accessed. For example, the RTL for lvehx contains this: eb <-- EA[60:63] if Big-Endian byte ordering then VRT[8*eb:8*eb+15] <-- MEM(EA,2) else VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2) This patch adds the element inversion, as described in the last line of the RTL. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-18Merge remote-tracking branch 'bonzini/configure' into stagingAnthony Liguori1-1/+1
# By Peter Maydell (3) and Ákos Kovács (2) # Via Paolo Bonzini * bonzini/configure: ui/Makefile.objs: delete unnecessary cocoa.o dependency default-configs/: CONFIG_GDBSTUB_XML removed Makefile.target: CONFIG_NO_* variables removed rules.mak: New string testing functions rules.mak: New logical functions for handling y/n values
2013-10-16Makefile.target: CONFIG_NO_* variables removedÁkos Kovács1-1/+1
CONFIG_NO_* variables replaced with the lnot logical function Signed-off-by: Ákos Kovács <akoskovacs@gmx.com> [PMM: fixed a few CONFIG_NO_* uses that were missed] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-10-11Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2-9/+5
# By Richard Henderson # Via Richard Henderson * rth/tcg-pull: exec: Add both big- and little-endian memory helpers tcg: Add qemu_ld_st_i32/64 tcg: Add TCGMemOp configure: Remove CONFIG_QEMU_LDST_OPTIMIZATION tcg: Add tcg-be-ldst.h tcg: Add tcg-be-null.h exec: Delete is_tcg_gen_code and GETRA_EXT tcg-aarch64: Update to helper_ret_*_mmu routines tcg: Merge tcg_register_helper into tcg_context_init tcg: Add tcg-runtime.c helpers to all_helpers tcg: Put target helper data into an array. tcg: Remove stray semi-colons from target-*/helper.h tcg: Move helper registration into tcg_context_init target-m68k: Rename helpers.h to helper.h tcg: Use a GHashTable for tcg_find_helper tcg: Delete tcg_helper_get_name declaration tcg-hppa: Remove tcg backend Message-id: 1381440525-6666-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-5/+5
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber1-3/+0
Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-20cpu: Move cpu state syncs up into cpu_dump_state()James Hogan1-2/+0
The x86 and ppc targets call cpu_synchronize_state() from their *_cpu_dump_state() callbacks to ensure that up to date state is dumped when KVM is enabled (for example when a KVM internal error occurs). Move this call up into the generic cpu_dump_state() function so that other KVM targets (namely MIPS) can take advantage of it. This requires kvm_cpu_synchronize_state() and cpu_synchronize_state() to be moved out of the #ifdef NEED_CPU_H in <sysemu/kvm.h> so that they're accessible to qom/cpu.c. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Alexander Graf <agraf@suse.de> Cc: Gleb Natapov <gleb@redhat.com> Cc: qemu-ppc@nongnu.org Cc: kvm@vger.kernel.org Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-1/+1
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand macros. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-03Merge branch 'tcg-next' of git://github.com/rth7680/qemuAurelien Jarno2-1/+3
* 'tcg-next' of git://github.com/rth7680/qemu: (29 commits) tcg-i386: Make use of zero-extended memory helper routines tcg: Introduce zero and sign-extended versions of load helpers exec: Split softmmu_defs.h target: Include softmmu_exec.h where forgotten exec: Rename USUFFIX to LSUFFIX tcg-i386: Don't perform GETPC adjustment in TCG code exec: Reorganize the GETRA/GETPC macros configure: Allow x32 as a host tcg-i386: Adjust tcg_out_tlb_load for x32 tcg-i386: Use intptr_t appropriately tcg: Fix jit debug for x32 tcg: Use appropriate types in tcg_reg_alloc_call tcg: Change tcg_out_ld/st offset to intptr_t tcg: Change tcg_gen_exit_tb argument to uintptr_t tcg: Use uintptr_t in TCGHelperInfo tcg: Change relocation offsets to intptr_t tcg: Change memory offsets to intptr_t tcg: Change frame pointer offsets to intptr_t tcg: Define TCG_ptr properly tcg: Define TCG_TYPE_PTR properly ...
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+2
Several targets forgot to include softmmu_exec.h, which would break them with a header cleanup to follow. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.1 at 2024-12-27 09:35:01 +0000