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| author | Tom Musta <tommusta@gmail.com> | 2013-11-01 08:21:12 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-12-20 01:57:53 +0100 |
| commit | fa1832d7e2fccfe3ea55d2885c023daa285342d4 (patch) | |
| tree | 4c55e3538440d89ca928740c5963b7a15040632b /target-ppc | |
| parent | cd73f2c992765141b3497551ebdf841b26c238ca (diff) | |
| download | qemu-fa1832d7e2fccfe3ea55d2885c023daa285342d4.zip qemu-fa1832d7e2fccfe3ea55d2885c023daa285342d4.tar.gz qemu-fa1832d7e2fccfe3ea55d2885c023daa285342d4.tar.bz2 | |
Add lxsdx
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index cf7927b..b5b3280 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7003,6 +7003,21 @@ static inline TCGv_i64 cpu_vsrl(int n) } } +static void gen_lxsdx(DisasContext *ctx) +{ + TCGv EA; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); + /* NOTE: cpu_vsrl is undefined */ + tcg_temp_free(EA); +} + static void gen_lxvd2x(DisasContext *ctx) { TCGv EA; @@ -9502,6 +9517,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), GEN_VAFORM_PAIRED(vsel, vperm, 21), GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), +GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |