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path: root/target-ppc/translate/vmx-impl.inc.c
AgeCommit message (Expand)AuthorFilesLines
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-1113/+0
2016-11-15target-ppc: Implement bcdctz. instructionJose Ricardo Ziviani1-0/+7
2016-11-15target-ppc: Implement bcdcfz. instructionJose Ricardo Ziviani1-0/+7
2016-11-15target-ppc: Implement bcdctn. instructionJose Ricardo Ziviani1-0/+4
2016-11-15target-ppc: Implement bcdcfn. instructionJose Ricardo Ziviani1-0/+55
2016-11-15target-ppc: add vprtyb[w/d/q] instructionsAnkit Kumar1-0/+3
2016-11-15target-ppc: add vrldnm and vrlwnm instructionsBharata B Rao1-0/+6
2016-11-15target-ppc: add vrldnmi and vrlwmi instructionsGautham R. Shenoy1-0/+6
2016-10-28target-ppc: add vmul10[u,eu,cu,ecu]q instructionsVasant Hegde1-0/+72
2016-10-28target-ppc: implement vnegw/d instructionsNikunj A Dadhania1-0/+2
2016-10-14target-ppc: implement vexts[bh]2w and vexts[bhw]2dNikunj A Dadhania1-0/+5
2016-10-05target-ppc: fix vmx instruction type/type2Nikunj A Dadhania1-15/+15
2016-10-05target-ppc: add vclzlsbb/vctzlsbb instructionsRajalakshmi Srinivasaraghavan1-0/+14
2016-10-05target-ppc: add vector compare not equal instructionsRajalakshmi Srinivasaraghavan1-1/+10
2016-09-23target-ppc: convert st64 to use new macroNikunj A Dadhania1-6/+6
2016-09-23target-ppc: convert ld64 to use new macroNikunj A Dadhania1-6/+6
2016-09-23target-ppc: add vector permute right indexed instructionRajalakshmi Srinivasaraghavan1-0/+18
2016-09-23target-ppc: add vector bit permute doubleword instructionRajalakshmi Srinivasaraghavan1-0/+1
2016-09-23target-ppc: add vector count trailing zeros instructionsRajalakshmi Srinivasaraghavan1-0/+19
2016-09-23target-ppc: add vector extract instructionsRajalakshmi Srinivasaraghavan1-0/+10
2016-09-23target-ppc: add vector insert instructionsRajalakshmi Srinivasaraghavan1-0/+32
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt1-0/+843
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