aboutsummaryrefslogtreecommitdiff
path: root/target-ppc/mmu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2015-03-09target-ppc: move sdr1 value change detection logic to helper_store_sdr1()Mark Cave-Ayland1-20/+15
2014-12-16qemu-log: add log category for MMU infoAntony Pavlov1-12/+14
2014-07-08PPC: Fix booke206 TLB with phys addrs > 32bitAlexander Graf1-3/+3
2014-06-16PPC: e500: Fix TLB lookup for 32bit CPUsAlexander Graf1-0/+5
2014-06-16PPC: e500: Fix MMUCSR0 emulationAlex Zuepke1-1/+1
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-2/+1
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-1/+1
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-16/+28
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-25/+33
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-22/+32
2014-03-13target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hookAndreas Färber1-1/+1
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-1/+1
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-4/+5
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber1-21/+22
2014-03-05target-ppc: Fix htab_mask calculationAneesh Kumar K.V1-1/+2
2013-09-03Merge branch 'tcg-next' of git://github.com/rth7680/qemuAurelien Jarno1-0/+2
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+2
2013-09-02target-ppc: Use #define instead of opencoding SLB valid bitAneesh Kumar K.V1-1/+1
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber1-1/+3
2013-07-09target-ppc: Change LOG_MMU_STATE() argument to CPUStateAndreas Färber1-3/+3
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber1-1/+1
2013-07-09target-ppc: Don't overuse ENV_GET_CPU()Andreas Färber1-1/+1
2013-07-01PPC: Fix GDB read on code area for PPC6xxFabien Chouteau1-1/+9
2013-07-01PPC: Add dump_mmu() for 6xxFabien Chouteau1-0/+92
2013-05-06PPC: Add MMU type for 2.06 with AMR but no TB pagesAlexander Graf1-0/+4
2013-03-22target-ppc: Use QOM method dispatch for MMU fault handlingDavid Gibson1-17/+7
2013-03-22target-ppc: Move ppc tlb_fill implementation into mmu_helper.cDavid Gibson1-2/+38
2013-03-22target-ppc: Split user only code out of mmu_helper.cDavid Gibson1-28/+0
2013-03-22target-ppc: mmu_ctx_t should not be a global typeDavid Gibson1-0/+13
2013-03-22target-ppc: Disentangle BAT code for 32-bit hash MMUsDavid Gibson1-34/+4
2013-03-22target-ppc: Don't share get_pteg_offset() between 32 and 64-bitDavid Gibson1-7/+2
2013-03-22target-ppc: Disentangle hash mmu helper functionsDavid Gibson1-7/+4
2013-03-22target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug()David Gibson1-13/+16
2013-03-22target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_faultDavid Gibson1-41/+16
2013-03-22target-ppc: Disentangle get_physical_address() pathsDavid Gibson1-38/+8
2013-03-22target-ppc: Rework get_physical_address()David Gibson1-46/+52
2013-03-22target-ppc: Disentangle get_segment()David Gibson1-101/+40
2013-03-22target-ppc: Disentangle find_pte()David Gibson1-114/+5
2013-03-22target-ppc: Disentangle pte_check()David Gibson1-55/+12
2013-03-22target-ppc: Move SLB handling into a mmu-hash64.cDavid Gibson1-195/+3
2013-03-22target-ppc: Remove address check for loggingDavid Gibson1-6/+4
2013-03-22target-ppc: Trivial cleanups in mmu_helper.cDavid Gibson1-8/+3
2013-03-22target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson1-39/+5
2013-02-01target-ppc: Fix target_ulong vs. hwaddr format mismatchesAndreas Färber1-3/+3
2013-02-01target-ppc: Fix unused variable warning for FLUSH_ALL_TLBSAndreas Färber1-1/+2
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-11-01target-ppc: make some functions staticBlue Swirl1-5/+6
2012-10-29Drop unnecessary check of TARGET_PHYS_ADDR_SPACE_BITSPeter Maydell1-2/+0