aboutsummaryrefslogtreecommitdiff
path: root/target-mips
AgeCommit message (Expand)AuthorFilesLines
2012-12-08Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl1-9/+10
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-06target-mips: Fix incorrect shift for SHILO and SHILOVPetar Jovanovic1-8/+9
2012-12-06target-mips: Fix incorrect code and test for INSVPetar Jovanovic1-1/+1
2012-11-24target-mips: remove POOL48A from the microMIPS decodingAurelien Jarno1-1/+0
2012-11-24target-mips: Clean up microMIPS32 major opcode陳韋任 (Wei-Ren Chen)1-7/+17
2012-11-24target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)1-0/+17
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-15target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)1-1/+1
2012-11-11target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson1-7/+11
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-11-05target-mips: use ULL for 64 bit constantsBlue Swirl1-2/+2
2012-11-01Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori1-5/+6
2012-10-31target-mips: don't flush extra TLB on permissions upgradeAurelien Jarno1-5/+23
2012-10-31target-mips: fix TLBR wrt SEGMaskAurelien Jarno1-0/+6
2012-10-31target-mips: use deposit instead of hardcoded versionAurelien Jarno1-28/+4
2012-10-31target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno1-48/+37
2012-10-31target-mips: implement movn/movz using movcondAurelien Jarno1-15/+12
2012-10-31target-mips: don't use local temps for store conditionalAurelien Jarno1-5/+6
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno3-159/+62
2012-10-31target-mips: simplify load/store microMIPS helpersAurelien Jarno1-64/+9
2012-10-31target-mips: optimize load operationsAurelien Jarno1-4/+12
2012-10-31target-mips: cleanup load/store operationsAurelien Jarno1-64/+35
2012-10-31target-mips: restore CPU state after an FPU exceptionAurelien Jarno1-90/+95
2012-10-31target-mips: use softfloat constants when possibleAurelien Jarno1-48/+44
2012-10-31target-mips: cleanup float to int conversion helpersAurelien Jarno1-39/+79
2012-10-31target-mips: fix FPU exceptionsAurelien Jarno1-13/+19
2012-10-31target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno1-63/+10
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno3-105/+64
2012-10-31target-mips: do not save CPU state when using retranslationAurelien Jarno1-20/+0
2012-10-31target-mips: correctly restore btarget upon exceptionAurelien Jarno1-0/+11
2012-10-31target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno1-36/+0
2012-10-31target-mips: Change TODO fileJia Liu1-2/+1
2012-10-31target-mips: Add ASE DSP processorsJia Liu1-0/+52
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu3-0/+995
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu3-0/+635
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu3-0/+311
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu3-0/+1499
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu3-0/+618
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu3-3/+1812
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu1-0/+88
2012-10-31target-mips: Add ASE DSP branch instructionsJia Liu1-0/+36
2012-10-31Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu1-27/+95
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu3-2/+47
2012-10-31target-mips: Add ASE DSP internal functionsJia Liu2-1/+1064
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-5/+6
2012-10-28target-mips: Use TCG registers for the FPU.Richard Henderson1-42/+54
generated by cgit v1.1 at 2024-11-02 13:21:27 +0000