| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson | 1 | -43/+5 |
| 2015-10-07 | tcg: Pass data argument to restore_state_to_opc | Richard Henderson | 1 | -4/+5 |
| 2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson | 1 | -1/+6 |
| 2015-10-07 | target-mips: Add delayed branch state to insn_start | Richard Henderson | 1 | -1/+2 |
| 2015-10-07 | target-*: Introduce and use cpu_breakpoint_test | Richard Henderson | 1 | -15/+10 |
| 2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson | 1 | -3/+2 |
| 2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson | 1 | -5/+4 |
| 2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson | 1 | -1/+1 |
| 2015-09-18 | target-mips: improve exception handling | Pavel Dovgaluk | 1 | -191/+174 |
| 2015-09-18 | target-mips: correct MTC0 instruction on MIPS64 | Leon Alrae | 1 | -11/+7 |
| 2015-09-18 | target-mips: add missing restriction in DAUI instruction | Leon Alrae | 1 | -1/+3 |
| 2015-09-18 | target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS | Aurelien Jarno | 1 | -39/+0 |
| 2015-09-18 | target-mips: get rid of MIPS_DEBUG | Aurelien Jarno | 1 | -605/+19 |
| 2015-09-18 | target-mips: remove wrong checks for recip.fmt and rsqrt.fmt | Petar Jovanovic | 1 | -4/+2 |
| 2015-09-18 | target-mips: Use tcg_gen_extrh_i64_i32 | Richard Henderson | 1 | -26/+22 |
| 2015-08-24 | tcg: Remove tcg_gen_trunc_i64_i32 | Richard Henderson | 1 | -2/+2 |
| 2015-08-13 | target-mips: simplify LWL/LDL mask generation | Aurelien Jarno | 1 | -8/+6 |
| 2015-08-04 | target-mips: Copy restrictions from ext/ins to dext/dins | Richard Henderson | 1 | -20/+25 |
| 2015-08-04 | target-mips: fix semihosting for microMIPS R6 | Leon Alrae | 1 | -3/+7 |
| 2015-07-15 | target-mips: fix page fault address for LWL/LWR/LDL/LDR | Aurelien Jarno | 1 | -0/+12 |
| 2015-07-15 | target-mips: fix logically dead code reported by Coverity | Leon Alrae | 1 | -0/+3 |
| 2015-06-26 | target-mips: microMIPS32 R6 POOL16{A, C} instructions | Yongbok Kim | 1 | -15/+118 |
| 2015-06-26 | target-mips: microMIPS32 R6 Major instructions | Yongbok Kim | 1 | -17/+45 |
| 2015-06-26 | target-mips: microMIPS32 R6 POOL32{I, C} instructions | Yongbok Kim | 1 | -6/+21 |
| 2015-06-26 | target-mips: microMIPS32 R6 POOL32F instructions | Yongbok Kim | 1 | -32/+199 |
| 2015-06-26 | target-mips: microMIPS32 R6 POOL32A{XF} instructions | Yongbok Kim | 1 | -10/+72 |
| 2015-06-26 | target-mips: microMIPS32 R6 branches and jumps | Yongbok Kim | 1 | -40/+202 |
| 2015-06-26 | target-mips: add microMIPS32 R6 opcode enum | Yongbok Kim | 1 | -16/+103 |
| 2015-06-26 | target-mips: signal RI for removed instructions in microMIPS R6 | Yongbok Kim | 1 | -0/+68 |
| 2015-06-26 | target-mips: raise RI exceptions when FIR.PS = 0 | Yongbok Kim | 1 | -33/+45 |
| 2015-06-26 | target-mips: rearrange gen_compute_compact_branch | Yongbok Kim | 1 | -236/+236 |
| 2015-06-26 | target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP | Yongbok Kim | 1 | -67/+99 |
| 2015-06-26 | target-mips: remove an unused argument | Yongbok Kim | 1 | -3/+2 |
| 2015-06-26 | target-mips: add microMIPS TLBINV, TLBINVF | Yongbok Kim | 1 | -0/+8 |
| 2015-06-26 | target-mips: fix {RD, WR}PGPR in microMIPS | Yongbok Kim | 1 | -2/+2 |
| 2015-06-26 | target-mips: add Unified Hosting Interface (UHI) support | Leon Alrae | 1 | -20/+55 |
| 2015-06-26 | target-mips: remove identical code in different branch | Leon Alrae | 1 | -21/+4 |
| 2015-06-22 | disas: Remove uses of CPU env | Peter Crosthwaite | 1 | -1/+1 |
| 2015-06-12 | target-mips: add MTHC0 and MFHC0 instructions | Leon Alrae | 1 | -0/+226 |
| 2015-06-12 | target-mips: add CP0.PageGrain.ELPA support | Leon Alrae | 1 | -1/+2 |
| 2015-06-12 | target-mips: extend selected CP0 registers to 64-bits in MIPS32 | Leon Alrae | 1 | -21/+42 |
| 2015-06-12 | target-mips: correct MFC0 for CP0.EntryLo in MIPS64 | Leon Alrae | 1 | -6/+6 |
| 2015-06-11 | target-mips: add ERETNC instruction and Config5.LLB bit | Leon Alrae | 1 | -5/+15 |
| 2015-06-11 | target-mips: Misaligned memory accesses for MSA | Yongbok Kim | 1 | -10/+17 |
| 2015-06-11 | target-mips: Misaligned memory accesses for R6 | Yongbok Kim | 1 | -12/+27 |
| 2015-06-11 | target-mips: add Config5.FRE support allowing Status.FR=0 emulation | Leon Alrae | 1 | -150/+158 |
| 2015-06-11 | target-mips: move group of functions above gen_load_fpr32() | Leon Alrae | 1 | -60/+58 |
| 2015-03-18 | target-mips: save cpu state before calling MSA load and store helpers | Leon Alrae | 1 | -0/+2 |
| 2015-03-18 | target-mips: fix hflags modified in delay / forbidden slot | Leon Alrae | 1 | -4/+15 |
| 2015-03-18 | target-mips: fix CP0.BadVAddr by stopping translation on Address Error | Leon Alrae | 1 | -0/+1 |
