riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-149/+0
2016-06-24	target-mips: Implement FCR31's R/W bitmask and related functionalities	Aleksandar Markovic	1	-5/+3
2016-05-19	qemu-common: push cpu.h inclusion out of qemu-common.h	Paolo Bonzini	1	-0/+1
2016-01-23	mips: Clean up includes	Peter Maydell	1	-1/+1
2014-12-16	target-mips: Add missing calls to synchronise SoftFloat status	Maciej W. Rozycki	1	-5/+3
2014-12-16	target-mips: gdbstub: Clean up FPU register handling	Maciej W. Rozycki	1	-19/+19
2014-12-16	target-mips: Correct the writes to Status and Cause registers via gdbstub	Maciej W. Rozycki	1	-2/+6
2014-12-16	target-mips: Make CP1.FIR read-only here too	Maciej W. Rozycki	1	-1/+1
2014-12-16	target-mips: Correct the handling of register #72 on writes	Maciej W. Rozycki	1	-1/+1
2014-11-03	target-mips: remove duplicated mips/ieee mapping function	Yongbok Kim	1	-7/+0
2013-07-27	cpu: Introduce CPUClass::gdb_{read,write}_register()	Andreas Färber	1	-2/+10
2013-07-27	gdbstub: Replace GET_REG() macros with gdb_get_reg() functions	Andreas Färber	1	-14/+17
2013-07-26	target-mips: Move cpu_gdb_{read,write}_register()	Andreas Färber	1	-0/+144