| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2008-07-23 | Less hardcoding of TARGET_USER_ONLY. | ths | 1 | -8/+1 |
| 2008-07-09 | Use temporary registers for the MIPS FPU emulation. | ths | 1 | -7/+1 |
| 2008-07-01 | Move interrupt_request and user_mode_only to common cpu state. | pbrook | 1 | -2/+0 |
| 2008-06-30 | Move CPU save/load registration to common code. | pbrook | 1 | -0/+2 |
| 2008-06-29 | Add instruction counter. | pbrook | 1 | -0/+6 |
| 2008-06-27 | More efficient target register / TC accesses. | ths | 1 | -37/+40 |
| 2008-06-24 | Remove remaining uses of T0 in the MIPS target. | ths | 1 | -3/+0 |
| 2008-06-24 | T1 is now dead. | ths | 1 | -1/+0 |
| 2008-06-11 | Move FP TNs to cpu env. | ths | 1 | -5/+6 |
| 2008-05-30 | Fix typo. | pbrook | 1 | -1/+1 |
| 2008-05-30 | Move clone() register setup to target specific code. Handle fork-like clone. | pbrook | 1 | -0/+10 |
| 2008-05-29 | Push common interrupt variables to cpu-defs.h (Glauber Costa) | bellard | 1 | -2/+0 |
| 2008-05-28 | moved halted field to CPU_COMMON | bellard | 1 | -2/+0 |
| 2008-05-28 | Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. | ths | 1 | -0/+1 |
| 2008-05-06 | Use TCG for MIPS GPR moves. | ths | 1 | -0/+1 |
| 2008-05-04 | Simplify mips branch handling. Retire T2 from use. Use TCG for branches. | ths | 1 | -1/+0 |
| 2008-02-12 | Make MIPS MT implementation more cache friendly. | ths | 1 | -4/+4 |
| 2007-12-30 | MIPS COP1X (and related) instructions, by Richard Sandiford. | ths | 1 | -7/+11 |
| 2007-12-26 | De-cruft exception definitions, and implement nicer debug output. | ths | 1 | -15/+12 |
| 2007-12-25 | Improved PABITS handling, and config register fixes. | ths | 1 | -0/+2 |
| 2007-11-10 | added cpu_model parameter to cpu_init() | bellard | 1 | -4/+2 |
| 2007-11-09 | Move kernel loader parameters from the cpu state to being board specific. | ths | 1 | -5/+0 |
| 2007-10-28 | Implement missing MIPS supervisor mode bits. | ths | 1 | -10/+16 |
| 2007-10-20 | Handle IBE on MIPS properly. | ths | 1 | -0/+3 |
| 2007-10-14 | Replace is_user variable with mmu_idx in softmmu core, | j_mayer | 1 | -0/+11 |
| 2007-10-12 | Unify '-cpu ?' option. | j_mayer | 1 | -0/+1 |
| 2007-09-27 | Move get_sp_from_cpustate from cpu.h to target_signal.h. | ths | 1 | -5/+0 |
| 2007-09-27 | linux-user sigaltstack() syscall, by Thayne Harbaugh. | ths | 1 | -0/+5 |
| 2007-09-25 | Optimise instructions accessing CP0, by Aurelien Jarno. | ths | 1 | -9/+10 |
| 2007-09-24 | Per-CPU instruction decoding implementation, by Aurelien Jarno. | ths | 1 | -0/+1 |
| 2007-09-06 | Partial support for 34K multithreading, not functional yet. | ths | 1 | -41/+198 |
| 2007-06-23 | Handle MIPS64 SEGBITS value correctly. | ths | 1 | -0/+2 |
| 2007-06-03 | Move target-specific defines to the target directories. | ths | 1 | -0/+6 |
| 2007-05-31 | Don't kill the registered irqs on reset. | ths | 1 | -3/+4 |
| 2007-05-30 | Fix CPU (re-)selection on reset. | ths | 1 | -1/+4 |
| 2007-05-29 | Fix usermode check, thanks Aurelien Jarno. | ths | 1 | -1/+1 |
| 2007-05-29 | Don't check the FPU state for each FPU instruction, use hflags to | ths | 1 | -3/+5 |
| 2007-05-28 | Handle PX/UX status flags correctly, by Aurelien Jarno. | ths | 1 | -0/+1 |
| 2007-05-23 | The 24k wants more watch and srsmap registers. | ths | 1 | -2/+2 |
| 2007-05-18 | - Move FPU exception handling into helper functions, since they are big. | ths | 1 | -3/+3 |
| 2007-05-13 | MIPS linux-user update. | ths | 1 | -0/+1 |
| 2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths | 1 | -8/+24 |
| 2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths | 1 | -19/+25 |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths | 1 | -0/+1 |
| 2007-04-07 | Unify IRQ handling. | pbrook | 1 | -0/+2 |
| 2007-04-05 | 64bit MIPS FPUs have 32 registers. | ths | 1 | -2/+1 |
| 2007-03-30 | Fix typo, suggested by Ben Taylor. | ths | 1 | -1/+1 |
| 2007-03-30 | Sanitize mips exception handling. | ths | 1 | -2/+0 |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths | 1 | -0/+2 |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths | 1 | -0/+5 |
