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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-05 23:14:23 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-05 23:14:23 +0000 |
| commit | f7cfb2a176208d3b5139a2e792b40edf1adb43b4 (patch) | |
| tree | e8d411ece526a47140f58225bfc4b7b751230783 /target-mips/cpu.h | |
| parent | fb82fea06403d7d7b064b9ef7acc9c62dcd52850 (diff) | |
| download | qemu-f7cfb2a176208d3b5139a2e792b40edf1adb43b4.zip qemu-f7cfb2a176208d3b5139a2e792b40edf1adb43b4.tar.gz qemu-f7cfb2a176208d3b5139a2e792b40edf1adb43b4.tar.bz2 | |
64bit MIPS FPUs have 32 registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 3849e50..4b17929 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -62,9 +62,8 @@ struct CPUMIPSState { target_ulong t2; #endif target_ulong HI, LO; - uint32_t DCR; /* ? */ /* Floating point registers */ - fpr_t fpr[16]; + fpr_t fpr[32]; #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) #define FPR_FD(cpu, n) (FPR(cpu, n)->fd) #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) |