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path: root/target-mips/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2015-03-11Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell1-2/+17
2015-03-11target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae1-0/+17
2015-03-11target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae1-2/+0
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-1/+0
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-0/+12
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki1-3/+5
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki1-3/+4
2014-12-16target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki1-0/+89
2014-12-16target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki1-4/+4
2014-11-07mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki1-0/+13
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim1-0/+4
2014-11-03target-mips: add MSA defines and data structureYongbok Kim1-2/+50
2014-11-03target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae1-1/+2
2014-11-03target-mips: implement forbidden slotLeon Alrae1-1/+2
2014-11-03target-mips: add Config5.SBRILeon Alrae1-2/+9
2014-11-03target-mips: update cpu_save/cpu_load to support new registersLeon Alrae1-1/+1
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae1-0/+6
2014-11-03target-mips: add TLBINV supportLeon Alrae1-0/+7
2014-11-03target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae1-1/+4
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-0/+4
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae1-0/+11
2014-11-03target-mips: add KScratch registersLeon Alrae1-0/+3
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim1-6/+7
2014-10-13target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae1-4/+14
2014-06-18target-mips: implement UserLocal RegisterPetar Jovanovic1-4/+7
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini1-0/+1
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell1-1/+1
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-0/+1
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-3/+2
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-28/+0
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic1-0/+10
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic1-0/+3
2013-12-02misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil1-1/+1
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-7/+0
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-13/+0
2013-06-28cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber1-2/+3
2013-05-20linux-user: Save the correct resume address for MIPS signal handlingKwok Cheung Yeung1-0/+1
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-1/+0
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-2/+2
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson1-0/+3
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber1-0/+1
2013-01-08target-mips: Allow DSP access to be disabled once enabled.Eric Johnson1-1/+1
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-3/+3
2012-11-01Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori1-5/+6
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu1-2/+21
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-5/+6
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity1-6/+6
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl1-8/+8
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