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2016-07-12target-*: Clean up cpu.h header guardsMarkus Armbruster1-3/+3
Most of them use guard symbols like CPU_$target_H, but we also have __MIPS_CPU_H__ and __TRICORE_CPU_H__. They all upset scripts/clean-header-guards.pl. The script dislikes CPU_$target_H because they don't match their file name (they should, to make guard collisions less likely). The others are reserved identifiers. Clean them all up: use guard symbol $target_CPU_H for target-$target/cpu.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12Fix confusing argument names in some common functionsSergey Sorokin1-1/+2
There are functions tlb_fill(), cpu_unaligned_access() and do_unaligned_access() that are called with access type and mmu index arguments. But these arguments are named 'is_write' and 'is_user' in their declarations. The patches fix the arguments to avoid a confusion. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1465907177-1399402-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-12target-mips: support CP0.Config4.AE bitPaul Burton1-0/+1
The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-07-12target-mips: change ASID type to hold more than 8 bitsPaul Burton1-1/+1
ASID currently has uint8_t type which is too small since some processors support more than 8 bits ASID. Therefore change its type to uint16_t. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-07-12target-mips: add ASID mask field and replace magic valuesPaul Burton1-0/+2
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-07-12target-mips: add exception base to MIPS CPULeon Alrae1-0/+2
Replace hardcoded 0xbfc00000 with exception_base which is initialized with this default address so there is no functional change here. However, it is now exposed and consequently it will be possible to modify it from outside of the CPU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-29Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-2/+0
* serial port fixes (Paolo) * Q35 modeling improvements (Paolo, Vasily) * chardev cleanup improvements (Marc-André) * iscsi bugfix (Peter L.) * cpu_exec patch from multi-arch patches (Peter C.) * pci-assign tweak (Lin Ma) # gpg: Signature made Wed 29 Jun 2016 15:56:30 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (35 commits) socket: unlink unix socket on remove socket: add listen feature char: clean up remaining chardevs when leaving vhost-user: disable chardev handlers on close vhost-user-test: fix g_cond_wait_until compat implementation vl: smp_parse: fix regression ich9: implement SCI_IRQ_SEL register ich9: implement ACPI_EN register serial: reinstate watch after migration serial: remove watch on reset char: change qemu_chr_fe_add_watch to return unsigned serial: separate serial_xmit and serial_watch_cb serial: simplify tsr_retry reset serial: make tsr_retry unsigned iscsi: fix assertion in is_sector_request_lun_aligned target-*: Don't redefine cpu_exec() pci-assign: Move "Invalid ROM" error message to pci-assign-load-rom.c vnc: generalize "VNC server running on ..." message scsi: esp: fix migration MC146818 RTC: add GPIO access to output IRQ ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-29target-*: Don't redefine cpu_exec()Peter Crosthwaite1-2/+0
This function needs to be converted to QOM hook and virtualised for multi-arch. This rename interferes, as cpu-qom will not have access to the renaming causing name divergence. This rename doesn't really do anything anyway so just delete it. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-Id: <69bd25a8678b8b31b91cd9760c777bed1aafb44e.1437212383.git.crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaitepeter@gmail.com>
2016-06-24target-mips: Add FCR31's FS bit definitionAleksandar Markovic1-1/+2
Add preprocessor definition of FCR31's FS bit, and update related code for setting this bit. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24target-mips: Implement FCR31's R/W bitmask and related functionalitiesAleksandar Markovic1-0/+8
This patch implements read and write access rules for Mips floating point control and status register (FCR31). The change can be divided into following parts: - Add fields that will keep FCR31's R/W bitmask in procesor definitions and processor float_status structure. - Add appropriate value for FCR31's R/W bitmask for each supported processor. - Add function for setting snan_bit_is_one, and integrate it in appropriate places. - Modify handling of CTC1 (case 31) instruction to use FCR31's R/W bitmask. - Modify handling user mode executables for Mips, in relation to the bit EF_MIPS_NAN2008 from ELF header, that is in turn related to reading and writing to FCR31. - Modify gdb behavior in relation to FCR31. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic1-0/+5
This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * cherry-picked 2 chunks from patch #2 to fix compilation warnings] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-2/+0
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19mips: move CP0 functions out of cpu.hPaolo Bonzini1-109/+4
These are here for historical reasons: they are needed from both gdbstub.c and op_helper.c, and the latter was compiled with fixed AREG0. It is not needed anymore, so uninline them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini1-16/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19target-mips: make cpu-qom.h not target specificPaolo Bonzini1-1/+37
Make MIPSCPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota1-1/+1
We are inconsistent with the type of tb->flags: usage varies loosely between int and uint64_t. Settle to uint32_t everywhere, which is superior to both: at least one target (aarch64) uses the most significant bit in the u32, and uint64_t is wasteful. Compile-tested for all targets. Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1460049562-23517-1-git-send-email-cota@braap.org>
2016-03-30target-mips: add MAAR, MAARI registerYongbok Kim1-0/+4
The MAAR register is a read/write register included in Release 5 of the architecture that defines the accessibility attributes of physical address regions. In particular, MAAR defines whether an instruction fetch or data load can speculatively access a memory region within the physical address bounds specified by MAAR. As QEMU doesn't do speculative access, hence this patch only provides ability to access the registers. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae1-1/+6
Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating the CACHE instruction as NOP. But since CACHE can operate on ITC Tags new MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when CACHE is in the ITC Access mode. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Configuration Tags and Storage CellsLeon Alrae1-0/+1
Implement ITC as a single object consisting of two memory regions: 1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which are accessible by the CPU via CACHE instruction. Also adding MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will dispatch reads/writes directly. 2) storage_io: memory-mapped ITC Storage whose address space is configurable (i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers. ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell has a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: add CPS to Malta boardLeon Alrae1-0/+1
If the user specifies smp > 1 and the CPU with CM GCR support, then create Coherent Processing System (which takes care of instantiating CPUs) rather than CPUs directly and connect i8259 and cbus to the pins exposed by CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use the same pin numbers as before. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30target-mips: add CMGCRBase registerYongbok Kim1-1/+2
Physical base address for the memory-mapped Coherency Manager Global Configuration Register space. The MIPS default location for the GCR_BASE address is 0x1FBF_8. This register only exists if Config3 CMGCR is set to one. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: move CMGCR enabling to a separate patch] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-23target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUsLeon Alrae1-0/+3
MIPS Release 6 and MIPS SIMD Architecture make it mandatory to have IEEE 754-2008 FPU which is indicated by CP1 FIR.HAS2008, FCSR.ABS2008 and FCSR.NAN2008 bits set to 1. In QEMU we still keep these bits cleared as there is no 2008-NaN support. However, this now causes problems preventing from running R6 Linux with the v4.5 kernel. Kernel refuses to execute 2008-NaN ELFs on a CPU whose FPU does not support 2008-NaN encoding: (...) VFS: Mounted root (ext4 filesystem) readonly on device 8:0. devtmpfs: mounted Freeing unused kernel memory: 256K (ffffffff806f0000 - ffffffff80730000) request_module: runaway loop modprobe binfmt-464c Starting init: /sbin/init exists but couldn't execute it (error -8) request_module: runaway loop modprobe binfmt-464c Starting init: /bin/sh exists but couldn't execute it (error -8) Kernel panic - not syncing: No working init found. Try passing init= option to kernel. See Linux Documentation/init.txt for guidance. Therefore always indicate presence of 2008-NaN support in R6 as well as in R5+MSA CPUs, even though this feature is not yet supported by MIPS in QEMU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-02-26target-mips: implement R6 multi-threadingYongbok Kim1-0/+25
MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-02-23all: Clean up includesPeter Maydell1-1/+0
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-02-19target-mips: Stop using uint_fast*_t types in r4k_tlb_t structPeter Maydell1-13/+13
The r4k_tlb_t structure uses the uint_fast*_t types. Most of these uses are in bitfields and are thus pointless, because the bitfield itself specifies the width of the type; just use 'unsigned int' instead. (On glibc uint_fast16_t is defined as either 32 or 64 bits, so we know the code is not reliant on it being exactly 16 bits.) There is also one use of uint_fast8_t, which we replace with uint8_t, because both are exactly 8 bits on glibc and this is the only place outside the softfloat code which uses an int_fast*_t type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2016-01-23target-mips/cpu.h: Fix spell errorDongxue Zhang1-1/+1
CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-11-24target-mips: flush QEMU TLB when disabling 64-bit addressingLeon Alrae1-1/+17
CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit Kernel/Supervisor/User Segments. If bit is cleared an access to corresponding segment should generate Address Error Exception. However, the guest may still be able to access some pages belonging to the disabled 64-bit segment because we forget to flush QEMU TLB. This patch fixes it. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-10-30target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim1-0/+1
Add Performance Counter (4) and XNP (5) register numbers to RDHWR. Add check_hwrena() to simplify access control checkings. Add RDHWR support to microMIPS R6. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-10-29target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6Leon Alrae1-1/+6
Implement the relationship between CP0.Status.KX, SX and UX. It should not be possible to set UX bit if SX is 0, the same applies for setting SX if KX is 0. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-10-29target-mips: move the test for enabled interrupts to a separate functionLeon Alrae1-14/+15
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson1-1/+0
This symbol no longer exists. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-mips: Add delayed branch state to insn_startRichard Henderson1-0/+1
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-25mips: Remove ELF_MACHINE from cpu.hPeter Crosthwaite1-2/+0
The only generic code relying on this is linux-user, but linux users' default behaviour of defaulting ELF_MACHINE to ELF_ARCH will handle this. The bootloaders can just pass EM_MIPS directly, as that is architecture specific code. This removes another architecture specific definition from the global namespace. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-By: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-18target-mips: improve exception handlingPavel Dovgaluk1-0/+24
This patch improves exception handling in MIPS. Instructions generate several types of exceptions. When exception is generated, it breaks the execution of the current translation block. Implementation of the exceptions handling does not correctly restore icount for the instruction which caused the exception. In most cases icount will be decreased by the value equal to the size of TB. This patch passes pointer to the translation block internals to the exception handler. It allows correct restoring of the icount value. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: avoid retranslation in linux-user SC, break lines which are over 80 chars, remove v3 changelog from the commit message] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-1/+1
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-13target-mips: update mips32r5-generic into P5600Yongbok Kim1-1/+1
As full specification of P5600 is available, mips32r5-generic should be renamed to P5600 and corrected as its intention. Correct PRid and detail of configuration. Features which are not currently supported are described as FIXME. Fix Config.MM bit location Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: correct cache line sizes and LLAddr shift] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite1-1/+1
Remove un-needed usages of ENV_GET_CPU() by converting the APIs to use CPUState pointers and retrieving the env_ptr as minimally needed. Scripted conversion for target-* change: for I in target-*/cpu.h; do sed -i \ 's/\(^int cpu_[^_]*_exec(\)[^ ][^ ]* \*s);$/\1CPUState *cpu);/' \ $I; done Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae1-0/+1
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae1-2/+25
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae1-7/+7
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-0/+1
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-2/+11
This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-03-11Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell1-2/+17
MIPS patches 2015-03-11 Changes: * use VMStateDescription for MIPS CPU # gpg: Signature made Wed Mar 11 15:01:52 2015 GMT using RSA key ID 0B29DA6B # gpg: Can't check signature: public key not found * remotes/lalrae/tags/mips-20150311: target-mips: add missing MSACSR and restore fp_status and hflags target-mips: replace cpu_save/cpu_load with VMStateDescription Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae1-0/+17
Save MSACSR state. Also remove fp_status, msa_fp_status, hflags and restore them in post_load() from the architectural registers. Float exception flags are not present in vmstate. Information they carry is used only by softfloat caller who translates them into MIPS FCSR.Cause, FCSR.Flags and then they are cleared. Therefore there is no need for saving them in vmstate. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-03-11target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae1-2/+0
Create VMStateDescription for MIPS CPU. The new structure contains exactly the same fields as before, therefore leaving existing version_id. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
Instead of making cpu_init() return CPUArchState, return CPUState. Changes were made using the Coccinelle semantic patch below. @@ typedef CPUState; identifier e; expression args; type CPUArchState; @@ - e = + cpu = cpu_init(args); - if (!e) { + if (!cpu) { ... } - cpu = ENV_GET_CPU(env); + e = cpu->env_ptr; @@ identifier new_env, new_cpu, env, cpu; type CPUArchState; expression args; @@ -{ - CPUState *cpu = ENV_GET_CPU(env); - CPUArchState *new_env = cpu_init(args); - CPUState *new_cpu = ENV_GET_CPU(new_env); +{ + CPUState *cpu = ENV_GET_CPU(env); + CPUState *new_cpu = cpu_init(args); + CPUArchState *new_env = new_cpu->env_ptr; ... } @@ identifier c, cpu_init_func, cpu_model; type StateType, CPUType; @@ -static inline StateType* cpu_init(const char *cpu_model) -{ - CPUType *c = cpu_init_func(cpu_model); ( - if (c == NULL) { - return NULL; - } - return &c->env; | - if (c) { - return &c->env; - } - return NULL; ) -} +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model)) @@ identifier cpu_init_func; identifier model; @@ -#define cpu_init(model) (&cpu_init_func(model)->env) +#define cpu_init(model) CPU(cpu_init_func(model)) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Max Filippov <jcmvbkbc@gmail.com> [AF: Fixed up cpu_copy() manually] Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-1/+0
The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-0/+12
Add missing calls to synchronise the SoftFloat status with the CP1.FSCR: + for the rounding and flush-to-zero modes upon processor reset, + for the flush-to-zero mode on FSCR updates through the GDB stub. Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE macro. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki1-3/+5
Make sure the address space is unconditionally wrapped on 32-bit processors, that is ones that do not implement at least the MIPS III ISA. Also make MIPS16 SAVE and RESTORE instructions use address calculation rather than plain arithmetic operations for stack pointer manipulation so that their semantics for stack accesses follows the architecture specification. That in particular applies to user software run on 64-bit processors with the CP0.Status.UX bit clear where the address space is wrapped to 32 bits. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki1-3/+4
Tighten ISA level checks down to MIPS II that many of our instructions are missing. Also make sure any 64-bit instruction enables are only applied to 64-bit processors, that is ones that implement at least the MIPS III ISA. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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